SPMU402 January   2026 LMK3H2104

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1Configuration Overview
    1. 1.1 LMK3H2104A09 Configuration Information
  4. 2Device Register Map
  5. 3Device Registers
  6. 4Revision History

2 Device Register Map

Table 2-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 2-1 should be considered as reserved locations and the register contents should not be modified.

Table 2-1 Register Map
Offset
(Hex)		Register
Acronym		Bit
76543210
0x0R0VENDOR_ID[7:0]
0x1R1VENDOR_ID[15:8]
0x2R2RESFLOAT_VDDO_3FLOAT_VDDO_2FLOAT_VDDO_1FLOAT_VDDO_0RESOTP_BURNT
0x3R3RESOTP_SEL_1_PU_RBOTP_SEL_0_PU_RBRES
0x4R4RESREF0_CTRL_PU_RBRES
0x5R5RESOTP_PAGE_SEL_DYN_DEBOUNCERES
0x6R6I2C_REG_ADDR_FMTI2C_TRGT_ADDR
0x8R8PWRGD_SAMPLE_TMR
0x9R9RESSUP_LVL_RAMP_TMRPWRGD_SAMPLE_TMR_EN
0xAR10GLOBAL_SUP_DET_TMR
0xBR11FOD0_PDBAW_PDAUTO_FOD_PD_ENCRC_IGNOREPIN_RESAMPLE_DISOTP_AUTOLOAD_DISPDNGLOBAL_SUP_DET_TMR_EN
0xCR12RESIN0_PDFOD1_PD
0xDR13PWRGD_PWRDN_PIN_SELRES
0xER14RESGPI0_FUNC
0xFR15RESGPI1_FUNC
0x10R16RESGPI2_FUNC
0x11R17RESOE_GLOBALRES
0x15R21RESGPIO0_FUNC
0x19R25RESGPIO1_FUNC
0x1AR26RESGPIO0_OUT_SRC_SEL
0x1CR28RESGPI2_POLARITYGPI1_POLARITYGPI0_POLARITYGPIO1_OUT_SRC_SEL
0x1DR29GPI0_PULL_DN_ENGPIO1_POLARITYRESGPIO0_POLARITYRES
0x1ER30RESGPI2_PULL_UP_ENGPI2_PULL_DN_ENRESGPI1_PULL_UP_ENGPI1_PULL_DN_ENGPI0_PULL_UP_EN
0x1FR31RESGPIO0_PULL_UP_ENGPIO0_PULL_DN_ENRES
0x20R32RESGPIO1_PULL_UP_ENGPIO1_PULL_DN_ENRES
0x21R33RESGPI2_LIVE_RBGPI1_LIVE_RBGPI0_LIVE_RBRES
0x22R34RESGPIO0_LIVE_RBRES
0x23R35RESGPIO1_GPO_VALRESGPIO0_GPO_VALGPIO1_LIVE_RBRES
0x24R36RESGPI1_OE_GRP_SELGPI0_OE_GRP_SEL
0x25R37RESGPI2_OE_GRP_SEL
0x27R39RESGPIO0_OE_GRP_SEL
0x29R41GPIO1_OUT_SIG_TYPERESGPIO0_OUT_SIG_TYPEGPIO1_OE_GRP_SEL
0x2AR42RESIN0_RCVR_FMT
0x2BR43RESIN0_TERMINATION_SEL
0x2CR44RESIN0_LOS_THRESHRESIN0_LOS_ENRES
0x2DR45PERST_BUF_IN0_STSRESPERST_BUF_IN0RES
0x2ER46RESPERST_BUF_IN0_LOS_ENRES
0x2FR47RESFOD0_N_DIV
0x30R48RESFOD1_N_DIV
0x31R49FOD0_NUM[7:0]
0x32R50FOD0_NUM[15:8]
0x33R51FOD0_NUM[23:16]
0x34R52FOD1_NUM[7:0]
0x35R53FOD1_NUM[15:8]
0x36R54FOD1_NUM[23:16]
0x37R55FOD1_CFG_UPDATEFOD0_CFG_UPDATEPATH1_DIVPATH0_DIV
0x39R57RESFOD_PH_OFFSET_N_DIV
0x3AR58FOD_PH_OFFSET_NUM[7:0]
0x3BR59FOD_PH_OFFSET_NUM[15:8]
0x3CR60RESFOD0_SSC_CONFIG_SELFOD0_SSC_MOD_TYPEFOD0_SSC_ENFOD_PH_OFFSET_FOD_SELFOD_PH_OFFSET_SHIFT_NOW
0x3DR61FOD0_SSC_STEPS[7:0]
0x3ER62RESFOD0_SSC_STEPS[12:8]
0x3FR63FOD0_DCO_STEP_SIZE[7:0]
0x40R64FOD0_DCO_STEP_SIZE[15:8]
0x41R65RESFOD1_SSC_CONFIG_SELFOD1_SSC_MOD_TYPEFOD1_SSC_EN
0x42R66FOD1_SSC_STEPS[7:0]
0x43R67RESFOD1_SSC_STEPS[12:8]
0x44R68FOD1_DCO_STEP_SIZE[7:0]
0x45R69FOD1_DCO_STEP_SIZE[15:8]
0x46R70RESFOD1_DCO_DECFOD1_DCO_INCFOD1_DCO_ENFOD0_DCO_DECFOD0_DCO_INCFOD0_DCO_EN
0x47R71FOD0_DCO_STEPS_STAT[7:0]
0x48R72FOD0_DCO_STEPS_STAT[15:8]
0x49R73FOD1_DCO_STEPS_STAT[7:0]
0x4AR74FOD1_DCO_STEPS_STAT[15:8]
0x4BR75RESFOD0_DCO_N_DIV_STAT
0x4CR76FOD0_DCO_NUM_STAT[7:0]
0x4DR77FOD0_DCO_NUM_STAT[15:8]
0x4ER78FOD0_DCO_NUM_STAT[23:16]
0x4FR79RESFOD1_DCO_N_DIV_STAT
0x50R80FOD1_DCO_NUM_STAT[7:0]
0x51R81FOD1_DCO_NUM_STAT[15:8]
0x52R82FOD1_DCO_NUM_STAT[23:16]
0x53R83BANK1_CLK_SELBANK0_CLK_SELPATH1_EDGE_COMB_ENPATH0_EDGE_COMB_EN
0x54R84RESBANK3_CLK_SELBANK2_CLK_SEL
0x55R85RESBANK5_CLK_SELBANK4_CLK_SEL
0x56R86BANK0_CH_DIV[7:0]
0x57R87BANK0_CH_DIV[15:8]
0x58R88BANK2_CH_DIVBANK1_CH_DIV
0x59R89RESIN0_LOS
0x5AR90BANK4_CH_DIVBANK3_CH_DIV
0x5BR91PERST_BUF_BANK1PERST_BUF_BANK0BANK5_CH_DIV
0x5CR92PERST_BUF_BANK5PERST_BUF_BANK4PERST_BUF_BANK3PERST_BUF_BANK2
0x5DR93BANK1_AUTO_CLK_SWITCHBACK_ENBANK0_AUTO_CLK_SWITCHBACK_ENBANK5_AUTO_CLK_SWITCHOVER_ENBANK4_AUTO_CLK_SWITCHOVER_ENBANK3_AUTO_CLK_SWITCHOVER_ENBANK2_AUTO_CLK_SWITCHOVER_ENBANK1_AUTO_CLK_SWITCHOVER_ENBANK0_AUTO_CLK_SWITCHOVER_EN
0x5ER94BANK3_AUTO_CLK_SWITCHOVER_CLK_SELBANK2_AUTO_CLK_SWITCHOVER_CLK_SELBANK1_AUTO_CLK_SWITCHOVER_CLK_SELBANK0_AUTO_CLK_SWITCHOVER_CLK_SELBANK5_AUTO_CLK_SWITCHBACK_ENBANK4_AUTO_CLK_SWITCHBACK_ENBANK3_AUTO_CLK_SWITCHBACK_ENBANK2_AUTO_CLK_SWITCHBACK_EN
0x5FR95BANK5_CLK_SWITCHOVER_TYPEBANK4_CLK_SWITCHOVER_TYPEBANK3_CLK_SWITCHOVER_TYPEBANK2_CLK_SWITCHOVER_TYPEBANK1_CLK_SWITCHOVER_TYPEBANK0_CLK_SWITCHOVER_TYPEBANK5_AUTO_CLK_SWITCHOVER_CLK_SELBANK4_AUTO_CLK_SWITCHOVER_CLK_SEL
0x60R96BANK1_SWITCHOVER_FRC_CLK_ENBANK0_SWITCHOVER_FRC_CLK_ENBANK5_CLK_DIS_ON_LOSBANK4_CLK_DIS_ON_LOSBANK3_CLK_DIS_ON_LOSBANK2_CLK_DIS_ON_LOSBANK1_CLK_DIS_ON_LOSBANK0_CLK_DIS_ON_LOS
0x61R97OUT1_SLEW_RATEOUT0_SLEW_RATEBANK5_SWITCHOVER_FRC_CLK_ENBANK4_SWITCHOVER_FRC_CLK_ENBANK3_SWITCHOVER_FRC_CLK_ENBANK2_SWITCHOVER_FRC_CLK_EN
0x62R98OUT3_SLEW_RATEOUT2_SLEW_RATERES
0x63R99OUT1_CMOS_SLEW_RATEOUT0_CMOS_SLEW_RATERES
0x64R100OUT3_CMOS_SLEW_RATEOUT2_CMOS_SLEW_RATERES
0x65R101OUT1_DIS_STATEOUT0_DIS_STATERES
0x66R102OUT3_DIS_STATEOUT2_DIS_STATERES
0x67R103OUT0_FMTREF1_DIS_STATEREF0_DIS_STATERES
0x68R104OUT2_FMTRESOUT1_FMT
0x69R105RESIN1_LOS
0x6AR106OUT1_CMOS_1P2V_ENOUT0_CMOS_1P2V_ENRESOUT3_FMT
0x6BR107RESOUT3_CMOS_1P2V_ENOUT2_CMOS_1P2V_ENRES
0x6CR108OUT1_OE_GRPOUT0_OE_GRP
0x6ER110OUT3_OE_GRPOUT2_OE_GRP
0x6FR111REF1_OE_GRPREF0_OE_GRP
0x70R112OUT1_LPHCSL_VOD_SELOUT0_LPHCSL_VOD_SEL
0x72R114OUT3_LPHCSL_VOD_SELOUT2_LPHCSL_VOD_SEL
0x74R116RESOUT1_SYNC_MODEOUT0_SYNC_MODE
0x75R117REF1_SYNC_MODEREF0_SYNC_MODEOUT3_SYNC_MODEOUT2_SYNC_MODE
0x76R118RESOUT1N_OE_CMOSOUT1P_OE_CMOSOUT0N_OE_CMOSOUT0P_OE_CMOSSINGLE_CMOS_EN_SYNC
0x77R119RESOUT3N_OE_CMOSOUT3P_OE_CMOSOUT2N_OE_CMOSOUT2P_OE_CMOSRES
0x78R120RESOUT3_FREQ_DET_ENOUT2_FREQ_DET_ENRESOUT1_FREQ_DET_ENOUT0_FREQ_DET_ENRES
0x7AR122OUT2_FREQ_DET_THRESHRESOUT1_FREQ_DET_THRESHOUT0_FREQ_DET_THRESHREF1_FREQ_DET_ENREF0_FREQ_DET_ENRES
0x7BR123RESOUT1_AMP_DET_ENOUT0_AMP_DET_ENREF1_FREQ_DET_THRESHREF0_FREQ_DET_THRESHRESOUT3_FREQ_DET_THRESH
0x7CR124OUT_AMP_DET_THRESHRESOUT3_AMP_DET_ENOUT2_AMP_DET_ENRES
0x7DR125CRC_ERROR_EVT_INTR_ENRESIN0_LOS_LMT_EVT_INTR_ENRESIN0_LOS_EVT_INTR_ENDEV_INTR
0x7ER126RESOUT1N_FREQ_ERR_EVT_INTR_ENOUT1P_FREQ_ERR_EVT_INTR_ENOUT0N_FREQ_ERR_EVT_INTR_ENOUT0P_FREQ_ERR_EVT_INTR_EN
0x7FR127RESOUT3N_FREQ_ERR_EVT_INTR_ENOUT3P_FREQ_ERR_EVT_INTR_ENOUT2N_FREQ_ERR_EVT_INTR_ENOUT2P_FREQ_ERR_EVT_INTR_EN
0x80R128RESOUT1N_AMP_ERR_EVT_INTR_ENOUT1P_AMP_ERR_EVT_INTR_ENOUT0N_AMP_ERR_EVT_INTR_ENOUT0P_AMP_ERR_EVT_INTR_ENREF1_FREQ_ERR_EVT_INTR_ENREF0_FREQ_ERR_EVT_INTR_EN
0x81R129RESOUT3N_AMP_ERR_EVT_INTR_ENOUT3P_AMP_ERR_EVT_INTR_ENOUT2N_AMP_ERR_EVT_INTR_ENOUT2P_AMP_ERR_EVT_INTR_ENRES
0x82R130RESIN0_LOS_EVTRES
0x83R131RESIN0_LOS_CNTR
0x84R132LOS_LMTRES
0x85R133OUT0N_FREQ_GOODOUT0P_FREQ_GOODCRC_ERROR_EVTCRC_ERRORCRC_DONERESIN0_LOS_LMT_EVT
0x86R134OUT2N_FREQ_GOODOUT2P_FREQ_GOODRESOUT1N_FREQ_GOODOUT1P_FREQ_GOOD
0x87R135REF1_FREQ_GOODREF0_FREQ_GOODRESOUT3N_FREQ_GOODOUT3P_FREQ_GOOD
0x88R136RESOUT1N_FREQ_ERR_EVTOUT1P_FREQ_ERR_EVTOUT0N_FREQ_ERR_EVTOUT0P_FREQ_ERR_EVT
0x89R137RESOUT3N_FREQ_ERR_EVTOUT3P_FREQ_ERR_EVTOUT2N_FREQ_ERR_EVTOUT2P_FREQ_ERR_EVT
0x8AR138RESOUT1N_AMP_GOODOUT1P_AMP_GOODOUT0N_AMP_GOODOUT0P_AMP_GOODREF1_FREQ_ERR_EVTREF0_FREQ_ERR_EVT
0x8BR139RESOUT3N_AMP_GOODOUT3P_AMP_GOODOUT2N_AMP_GOODOUT2P_AMP_GOODRES
0x8CR140OUT1N_AMP_ERR_EVTOUT1P_AMP_ERR_EVTOUT0N_AMP_ERR_EVTOUT0P_AMP_ERR_EVTRES
0x8DR141OUT3N_AMP_ERR_EVTOUT3P_AMP_ERR_EVTOUT2N_AMP_ERR_EVTOUT2P_AMP_ERR_EVTRES
0x8FR143RESPROD_REV_ID
0x90R144OTP_ID
0x93R147UNLOCK_PROTECTED_REG
0x94R148RESVDDD_SUP_LVL_DET_RBVDDA_SUP_LVL_DET_RB
0x95R149VDDO_3_SUP_LVL_DET_RBVDDO_2_SUP_LVL_DET_RBVDDO_1_SUP_LVL_DET_RBVDDO_0_SUP_LVL_DET_RB
0x96R150RESVDD_REF_SUP_LVL_DET_RBRES
0xBBR187CRC_COMPUTED
0xBCR188RESBOOTOSC_CLK_DISRES
0xFDR253RESPAGE_SEL_0
0x13FR319RESCLK_READY
0x240R576RESOUT0_DIS
0x244R580RESOUT1_DIS
0x250R592RESOUT2_DIS
0x254R596RESOUT3_DIS
0x258R600RESREF0_DIS
0x25CR604RESREF1_DIS
0x270R624RESPATH1_FOD_SELRES
0x2E9R745RESOUT1P_INV_POLOUT0P_INV_POLRES
0x2EAR746RESOUT1N_INV_POLOUT0N_INV_POLRESOUT3P_INV_POLOUT2P_INV_POLRES
0x2EBR747RESOUT3N_INV_POLOUT2N_INV_POLRES
0x2FAR762DIE_ID_1[7:0]
0x2FBR763RESDIE_ID_1[14:8]
0x2FCR764DIE_ID_2[7:0]
0x2FER766DIE_ID_2[15:8]
0x2FFR767DIE_ID_3[7:0]
0x300R768DIE_ID_3[15:8]
0x301R769RESALTERNATE_OE_SEL
0x302R770STORED_CRC