SPMU398 User guide | 德州仪器 TI.com.cn

SPMU398 January 2026 LMK3H2104

1.1 LMK3H2104A01 Configuration Information

Table 1-1 Frequency Configuration

OTP Page	OUT0 (MHz)	OUT1 (MHz)	OUT2 (MHz)	OUT3 (MHz)	REF0 (MHz)	REF1 (MHz)
OTP Page 0	100	100	100	100	Disabled	Disabled
OTP Page 1	100	100	100	100	Disabled	Disabled
OTP Page 2	100	100	100	100	Disabled	Disabled
OTP Page 3	100	100	100	100	Disabled	Disabled

Table 1-2 I2C Configuration

OTP Page	I2C Configuration
OTP Page 0	I2C Address: 0x69 1 Byte Register Addressing
OTP Page 1	I2C Address: 0x69 1 Byte Register Addressing
OTP Page 2	I2C Address: 0x69 1 Byte Register Addressing
OTP Page 3	I2C Address: 0x69 1 Byte Register Addressing

Table 1-3 GPI Settings, OTP Page 0

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Inverted	Enabled	Disabled
GPI1	GPI	Inverted	Enabled	Disabled
GPI2	Alternative OE Mapping 1	Inverted	Disabled	Disabled

Table 1-4 GPIO Settings, OTP Page 0

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Alternative OE Mapping 1	Inverted	Disabled	Disabled
GPIO1	GPI	Inverted	Disabled	Disabled

Table 1-5 Input Settings, OTP Page 0

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Powered Down	N/A (NI0 Unused)	None, DC

Table 1-6 Output Settings, OTP Page 0

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT1	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT2	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT3	100	DC-LVDS	PATH1	Enabled	No OE Group	Disabled
REF0	Disabled	N/A	PATH1	Disabled	No OE Group	Disabled
REF1	Disabled	N/A	PATH1	Disabled	No OE Group	Disabled

Table 1-7 GPI Settings, OTP Page 1

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Inverted	Enabled	Disabled
GPI1	GPI	Inverted	Enabled	Disabled
GPI2	Alternative OE Mapping 1	Inverted	Disabled	Disabled

Table 1-8 GPIO Settings, OTP Page 1

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Alternative OE Mapping 1	Inverted	Disabled	Disabled
GPIO1	GPI	Inverted	Disabled	Disabled

Table 1-9 Input Settings, OTP Page 1

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Powered Down	N/A (NI0 Unused)	None, DC

Table 1-10 Output Settings, OTP Page 1

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT1	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT2	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT3	100	DC-LVDS	PATH1	Enabled	No OE Group	Disabled
REF0	Disabled	N/A	PATH1	Disabled	No OE Group	Disabled
REF1	Disabled	N/A	PATH1	Disabled	No OE Group	Disabled

Table 1-11 GPI Settings, OTP Page 2

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Inverted	Enabled	Disabled
GPI1	GPI	Inverted	Enabled	Disabled
GPI2	Alternative OE Mapping 1	Inverted	Disabled	Disabled

Table 1-12 GPIO Settings, OTP Page 2

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Alternative OE Mapping 1	Inverted	Disabled	Disabled
GPIO1	GPI	Inverted	Disabled	Disabled

Table 1-13 Input Settings, OTP Page 2

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Powered Down	N/A (NI0 Unused)	None, DC

Table 1-14 Output Settings, OTP Page 2

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT1	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT2	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT3	100	DC-LVDS	PATH1	Enabled	No OE Group	Disabled
REF0	Disabled	N/A	PATH1	Disabled	No OE Group	Disabled
REF1	Disabled	N/A	PATH1	Disabled	No OE Group	Disabled

Table 1-15 GPI Settings, OTP Page 3

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Inverted	Enabled	Disabled
GPI1	GPI	Inverted	Enabled	Disabled
GPI2	Alternative OE Mapping 1	Inverted	Disabled	Disabled

Table 1-16 GPIO Settings, OTP Page 3

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Alternative OE Mapping 1	Inverted	Disabled	Disabled
GPIO1	GPI	Inverted	Disabled	Disabled

Table 1-17 Input Settings, OTP Page 3

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Powered Down	N/A (NI0 Unused)	None, DC

Table 1-18 Output Settings, OTP Page 3

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT1	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT2	100	85 Ω LP-HCSL	PATH1	Enabled	No OE Group	Disabled
OUT3	100	DC-LVDS	PATH1	Enabled	No OE Group	Disabled
REF0	Disabled	N/A	PATH1	Disabled	No OE Group	Disabled
REF1	Disabled	N/A	PATH1	Disabled	No OE Group	Disabled