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  1.   Trademarks
  2. 1Introduction
  3. 2Pulse Width Modulation (PWM) emulation of a DAC
  4. 3Audio Sampling Rate and Resolution Analysis
    1. 3.1 Using the PWM DAC Method
    2. 3.2 Using Off-Chip DAC
  5. 4Audio File Data Format
    1. 4.1 WAV File Size Calculation
    2. 4.2 Storing WAV Audio on Internal Flash
  6. 5Hardware Setup
    1. 5.1 BOOSTXL-AUDIO BoosterPack Overview
    2. 5.2 Hardware Setup for EK-TM4C1294XL
    3. 5.3 Hardware Setup for EK-TM4C123GXL
    4. 5.4 Hardware Setup for DK-TM4C129x Development Board
  7. 6Application Examples
    1. 6.1 Examples: audio_playback_internal_wavefile_by_PWM_EKTM4C129 and audio_playback_internal_wavefile_by_SPIDAC_EKTM4C129
    2. 6.2 Examples: audio_playback_internal_wavefile_by_PWM_EKTM4C123 and audio_playback_internal_wavefile_by_SPIDAC_EKTM4C123
    3. 6.3 Examples: audio_playback_internal_wavefile_by_PWM and audio_playback_internal_wavefile_by_SPIDAC
    4. 6.4 Examples: audio_playback_with_sdcard_by_PWM and audio_playback_with_sdcard_by_SPIDAC
  8. 7Download and Import the Examples
  9. 8References

Using the PWM DAC Method

It is understood that a CD quality audio is digitized at a 44.1 kHz sampling rate with 16-bit resolution. The question to then ask is can an MCU achieve this sampling rate and resolution during playback using the PWM DAC method?

To achieve the audio sampling rate during playback, MCU can create a simple timer at the expected frequency. At each timer interrupt, a PWM is generated for the required duty cycle at the desired resolution. This is straight forward for most microcontrollers. Normally the desired sampling rate can be generated by dividing from the timer’s timebase. If the desired sampling rate is integer divisible by the timebase, then the sampling rate can be fully achieved. For sampling rates that are not fully integer divisible, MCU can still reach the desired sampling rate at very high accuracy. Table 3-1 column C shows the achieved sampling rates when the timer uses SYSCLK as the timebase operating at 120 Mhz. As can be seen, for sampling rates at 22.05 kHz and 44.1 kHz, the achieved sampling rates are within 0.00% of the expected. In another word, MCU will be playing back the audio at three decimal points faster than the expected playback speed. For a non-audiophile person, this is not discernible.

To achieve the desired resolution is a different story. For 16-bit resolution, it means there are 216 = 65536 discrete steps. In another word, to achieve 16-bit resolution, PWM must be able to vary its duty cycle at the granularity of 1/65536 of a PWM period in order to achieve a 16-bit DAC equivalent. This is evidently not possible as shown in the second column of Table 3-1 where there are only 2721 SYSCLK cycles in a 44.1 kHz PWM period.

The maximum achievable resolution at the respective sampling rate by MCU can be calculated by the equation as shown in Equation 2:

Equation 2. Achievable Resolution = Log2(Number of timebase clocks in one PWM period)

Fifth column shows the maximum achieved resolution at the respective sampling rate. For 44.1 kHz the achieved resolution is 11.41. Like most microcontrollers, TM4C12x MCUs cannot achieve 16-bit resolution using PWM DAC method, but 8-bit audio resolution is certainly achievable.

Sixth and Seventh columns show the minimum timebase frequency that is required to achieve either 16-bit or 8-bit resolution for different desired sample rates.

Table 3-2 shows the analysis for TM4C123x MCU operating at maximum 80 Mhz.

Table 3-1 Sampling Rate and Resolution Analysis for TM4C192x MCU
Desired Sample Rate Number of System Clocks at 120 Mhz Achieved Sample Rate Error in Achieved Sample Rate Achieved Resolution Minimum SYSCLK (Mhz) Required to Achieve 16-Bit Resolution Minimum SYSCLK (Mhz) Required to Achieve 8-Bit Resolution
8000 15000 8000.00 0.00% 13.87 524.29 2.05
16000 7500 16000.00 0.00% 12.87 1048.58 4.10
22050

5442

22050.72

0.00% 12.41

1445.07

5.64
44100

2721

44101.43

0.00% 11.41

2890.14

11.29
48000 2500 48000.00 0.00% 11.29 3145.73 12.29
Table 3-2 Sampling Rate and Resolution Analysis for TM4C123x MCU
Desired Sample Rate Number of System Clocks at 80 Mhz Achieved Sample Rate Error in Achieved Sample Rate Achieved Resolution Minimum SYSCLK (Mhz) Required to Achieve 16-Bit Resolution Minimum SYSCLK (Mhz) Required to Achieve 8-Bit Resolution
8000 10000 8000.00 0.00% 13.29 524.29 2.05
16000 5000 16000.00 0.00% 12.29 1048.58 4.10
22050

3628

22050.75

0.00% 11.82

1445.07

5.64
44100

1814

44101.43

0.00% 10.82

2890.14

11.29

48000 1666 48019.21 0.04% 10.70 3145.73 12.29

Although it is not possible to achieve 16-bit resolution, it is still possible to generate the equivalent duty cycle ratio at the maximum achievable resolution for MCU by scaling. For example, if the audio file digitizes a sample point with a value of 0x1234 as a 16-bit value at 44.1 kHz sampling rate, the duty cycle ratio is equal to 0x1234 / 0xFFFF = 7.1%. The TM4C129x PWM counter would be configured with 2721 to generate a PWM period that is equal to 44.1 kHz and the match value would be configured to 7.1% x 2721 = 193 to generate the high phase of the duty cycle.

The PWM method is a low-cost way to emulate digital-to-analog conversion for most microcontrollers. For audio applications requiring only 8-bit resolution, PWM DAC method is certainly a viable option. For high quality audio applications, some loss of fidelity is expected.