SNVU926 User guide | 德州仪器 TI.com.cn

SNVU926 October 2024 LP5810

2.13 LED_2_Autonomous_Animation Registers

Table 2-110 lists the memory-mapped registers for the LED_2_Autonomous_Animation registers. All register offset addresses not listed in Table 2-110 should be considered as reserved locations and the register contents should not be modified.

Table 2-110 LED_2_AUTONOMOUS_ANIMATION Registers

Offset	Acronym	Register Name	Section
B4h	LED_2_Auto_Pause	Animation pause time at the start and the end of LED_2	Go
B5h	LED_2_Auto_Playback	Animation pattern playback times of LED_2 and active AEU number setting	Go
B6h	LED_2_AEU1_PWM_1	PWM setting of LED_2 AEU1_PWM1	Go
B7h	LED_2_AEU1_PWM_2	PWM setting of LED_2 AEU1_PWM2	Go
B8h	LED_2_AEU1_PWM_3	PWM setting of LED_2 AEU1_PWM3	Go
B9h	LED_2_AEU1_PWM_4	PWM setting of LED_2 AEU1_PWM4	Go
BAh	LED_2_AEU1_PWM_5	PWM setting of LED_2 AEU1_PWM5	Go
BBh	LED_2_AEU1_T12	Slope time setting of LED_2 AEU1_T1 and AEU1_T2	Go
BCh	LED_2_AEU1_T34	Slope time setting of LED_2 AEU1_T3 and AEU1_T4	Go
BDh	LED_2_AEU1_Playback	AEU1 pattern playback times of LED_2	Go
BEh	LED_2_AEU2_PWM_1	PWM setting of LED_2 AEU2_PWM1	Go
BFh	LED_2_AEU2_PWM_2	PWM setting of LED_2 AEU2_PWM2	Go
C0h	LED_2_AEU2_PWM_3	PWM setting of LED_2 AEU2_PWM3	Go
C1h	LED_2_AEU2_PWM_4	PWM setting of LED_2 AEU2_PWM4	Go
C2h	LED_2_AEU2_PWM_5	PWM setting of LED_2 AEU2_PWM5	Go
C3h	LED_2_AEU2_T12	Slope time setting of LED_2 AEU2_T1 and AEU2_T2	Go
C4h	LED_2_AEU2_T34	Slope time setting of LED_2 AEU2_T3 and AEU2_T4	Go
C5h	LED_2_AEU2_Playback	AEU2 pattern playback times of LED_2	Go
C6h	LED_2_AEU3_PWM_1	PWM setting of LED_2 AEU3_PWM1	Go
C7h	LED_2_AEU3_PWM_2	PWM setting of LED_2 AEU3_PWM2	Go
C8h	LED_2_AEU3_PWM_3	PWM setting of LED_2 AEU3_PWM3	Go
C9h	LED_2_AEU3_PWM_4	PWM setting of LED_2 AEU3_PWM4	Go
CAh	LED_2_AEU3_PWM_5	PWM setting of LED_2 AEU3_PWM5	Go
CBh	LED_2_AEU3_T12	Slope time setting of LED_2 AEU3_T1 and AEU3_T2	Go
CCh	LED_2_AEU3_T34	Slope time setting of LED_2 AEU3_T3 and AEU3_T4	Go
CDh	LED_2_AEU3_Playback	AEU3 pattern playback times of LED_2	Go

Complex bit access types are encoded to fit into small table cells. Table 2-111 shows the codes that are used for access types in this section.

Table 2-111 LED_2_Autonomous_Animation Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

2.13.1 LED_2_Auto_Pause Register (Offset = B4h) [Reset = 00h]

LED_2_Auto_Pause is shown in Figure 2-87 and described in Table 2-112.

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Figure 2-87 LED_2_Auto_Pause Register

7	6	5	4	3	2	1	0
led_2_tp_ts				led_2_tp_te
R/W-0h				R/W-0h

Table 2-112 LED_2_Auto_Pause Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	led_2_tp_ts	R/W	0h	Animation pause time at the start of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;
3-0	led_2_tp_te	R/W	0h	Animation pause time at the end of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;

2.13.2 LED_2_Auto_Playback Register (Offset = B5h) [Reset = 00h]

LED_2_Auto_Playback is shown in Figure 2-88 and described in Table 2-113.

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Figure 2-88 LED_2_Auto_Playback Register

7	6	5	4	3	2	1	0
RESERVED		led_2_aeu_num		led_2_pt
R-0h		R/W-0h		R/W-0h

Table 2-113 LED_2_Auto_Playback Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	Reserved
5-4	led_2_aeu_num	R/W	0h	Active AEU number of LED_2 selection; 0h = only use AEU1; 1h = use AEU1 and AEU2; 2h = use AEU1, AEU2 and AEU3; 3h = use AEU1, AEU2 and AEU3 (the same as 2h)
3-0	led_2_pt	R/W	0h	Animation pattern playback times of LED_2; 0h = 0 times; 1h = 1 times; 2h = 2 times; 3h = 3 times; 4h = 4 times; 5h = 5 times; 6h = 6 times; 7h = 7 times; 8h = 8 times; 9h = 9 times; Ah = 10 times; Bh = 11 times; Ch = 12 times; Dh = 13 times; Eh = 14 times; Fh = infinite times

2.13.3 LED_2_AEU1_PWM_1 Register (Offset = B6h) [Reset = 00h]

LED_2_AEU1_PWM_1 is shown in Figure 2-89 and described in Table 2-114.

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Figure 2-89 LED_2_AEU1_PWM_1 Register

7	6	5	4	3	2	1	0
led_2_aeu1_pwm1
R/W-0h

Table 2-114 LED_2_AEU1_PWM_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu1_pwm1	R/W	0h	AEU1_PWM1 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.4 LED_2_AEU1_PWM_2 Register (Offset = B7h) [Reset = 00h]

LED_2_AEU1_PWM_2 is shown in Figure 2-90 and described in Table 2-115.

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Figure 2-90 LED_2_AEU1_PWM_2 Register

7	6	5	4	3	2	1	0
led_2_aeu1_pwm2
R/W-0h

Table 2-115 LED_2_AEU1_PWM_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu1_pwm2	R/W	0h	AEU1_PWM2 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.5 LED_2_AEU1_PWM_3 Register (Offset = B8h) [Reset = 00h]

LED_2_AEU1_PWM_3 is shown in Figure 2-91 and described in Table 2-116.

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Figure 2-91 LED_2_AEU1_PWM_3 Register

7	6	5	4	3	2	1	0
led_2_aeu1_pwm3
R/W-0h

Table 2-116 LED_2_AEU1_PWM_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu1_pwm3	R/W	0h	AEU1_PWM3 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.6 LED_2_AEU1_PWM_4 Register (Offset = B9h) [Reset = 00h]

LED_2_AEU1_PWM_4 is shown in Figure 2-92 and described in Table 2-117.

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Figure 2-92 LED_2_AEU1_PWM_4 Register

7	6	5	4	3	2	1	0
led_2_aeu1_pwm4
R/W-0h

Table 2-117 LED_2_AEU1_PWM_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu1_pwm4	R/W	0h	AEU1_PWM4 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.7 LED_2_AEU1_PWM_5 Register (Offset = BAh) [Reset = 00h]

LED_2_AEU1_PWM_5 is shown in Figure 2-93 and described in Table 2-118.

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Figure 2-93 LED_2_AEU1_PWM_5 Register

7	6	5	4	3	2	1	0
led_2_aeu1_pwm5
R/W-0h

Table 2-118 LED_2_AEU1_PWM_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu1_pwm5	R/W	0h	AEU1_PWM5 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.8 LED_2_AEU1_T12 Register (Offset = BBh) [Reset = 00h]

LED_2_AEU1_T12 is shown in Figure 2-94 and described in Table 2-119.

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Figure 2-94 LED_2_AEU1_T12 Register

7	6	5	4	3	2	1	0
led_2_aeu1_t2				led_2_aeu1_t1
R/W-0h				R/W-0h

Table 2-119 LED_2_AEU1_T12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	led_2_aeu1_t2	R/W	0h	AEU1_T2 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;
3-0	led_2_aeu1_t1	R/W	0h	AEU1_T1 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;

2.13.9 LED_2_AEU1_T34 Register (Offset = BCh) [Reset = 00h]

LED_2_AEU1_T34 is shown in Figure 2-95 and described in Table 2-120.

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Figure 2-95 LED_2_AEU1_T34 Register

7	6	5	4	3	2	1	0
led_2_aeu1_t4				led_2_aeu1_t3
R/W-0h				R/W-0h

Table 2-120 LED_2_AEU1_T34 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	led_2_aeu1_t4	R/W	0h	AEU1_T4 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;
3-0	led_2_aeu1_t3	R/W	0h	AEU1_T3 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;

2.13.10 LED_2_AEU1_Playback Register (Offset = BDh) [Reset = 00h]

LED_2_AEU1_Playback is shown in Figure 2-96 and described in Table 2-121.

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Figure 2-96 LED_2_AEU1_Playback Register

7	6	5	4	3	2	1	0
RESERVED						led_2_aeu1_pt
R-0h						R/W-0h

Table 2-121 LED_2_AEU1_Playback Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1-0	led_2_aeu1_pt	R/W	0h	AEU1 pattern playback times of LED_2; 0h = 0 time; 1h = 1 time; 2h = 2 times; 3h = Infinite times

2.13.11 LED_2_AEU2_PWM_1 Register (Offset = BEh) [Reset = 00h]

LED_2_AEU2_PWM_1 is shown in Figure 2-97 and described in Table 2-122.

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Figure 2-97 LED_2_AEU2_PWM_1 Register

7	6	5	4	3	2	1	0
led_2_aeu2_pwm1
R/W-0h

Table 2-122 LED_2_AEU2_PWM_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu2_pwm1	R/W	0h	AEU2_PWM1 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.12 LED_2_AEU2_PWM_2 Register (Offset = BFh) [Reset = 00h]

LED_2_AEU2_PWM_2 is shown in Figure 2-98 and described in Table 2-123.

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Figure 2-98 LED_2_AEU2_PWM_2 Register

7	6	5	4	3	2	1	0
led_2_aeu2_pwm2
R/W-0h

Table 2-123 LED_2_AEU2_PWM_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu2_pwm2	R/W	0h	AEU2_PWM2 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.13 LED_2_AEU2_PWM_3 Register (Offset = C0h) [Reset = 00h]

LED_2_AEU2_PWM_3 is shown in Figure 2-99 and described in Table 2-124.

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Figure 2-99 LED_2_AEU2_PWM_3 Register

7	6	5	4	3	2	1	0
led_2_aeu2_pwm3
R/W-0h

Table 2-124 LED_2_AEU2_PWM_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu2_pwm3	R/W	0h	AEU2_PWM3 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.14 LED_2_AEU2_PWM_4 Register (Offset = C1h) [Reset = 00h]

LED_2_AEU2_PWM_4 is shown in Figure 2-100 and described in Table 2-125.

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Figure 2-100 LED_2_AEU2_PWM_4 Register

7	6	5	4	3	2	1	0
led_2_aeu2_pwm4
R/W-0h

Table 2-125 LED_2_AEU2_PWM_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu2_pwm4	R/W	0h	AEU2_PWM4 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.15 LED_2_AEU2_PWM_5 Register (Offset = C2h) [Reset = 00h]

LED_2_AEU2_PWM_5 is shown in Figure 2-101 and described in Table 2-126.

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Figure 2-101 LED_2_AEU2_PWM_5 Register

7	6	5	4	3	2	1	0
led_2_aeu2_pwm5
R/W-0h

Table 2-126 LED_2_AEU2_PWM_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu2_pwm5	R/W	0h	AEU2_PWM5 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.16 LED_2_AEU2_T12 Register (Offset = C3h) [Reset = 00h]

LED_2_AEU2_T12 is shown in Figure 2-102 and described in Table 2-127.

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Figure 2-102 LED_2_AEU2_T12 Register

7	6	5	4	3	2	1	0
led_2_aeu2_t2				led_2_aeu2_t1
R/W-0h				R/W-0h

Table 2-127 LED_2_AEU2_T12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	led_2_aeu2_t2	R/W	0h	AEU2_T2 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;
3-0	led_2_aeu2_t1	R/W	0h	AEU2_T1 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;

2.13.17 LED_2_AEU2_T34 Register (Offset = C4h) [Reset = 00h]

LED_2_AEU2_T34 is shown in Figure 2-103 and described in Table 2-128.

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Figure 2-103 LED_2_AEU2_T34 Register

7	6	5	4	3	2	1	0
led_2_aeu2_t4				led_2_aeu2_t3
R/W-0h				R/W-0h

Table 2-128 LED_2_AEU2_T34 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	led_2_aeu2_t4	R/W	0h	AEU2_T4 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;
3-0	led_2_aeu2_t3	R/W	0h	AEU2_T3 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;

2.13.18 LED_2_AEU2_Playback Register (Offset = C5h) [Reset = 00h]

LED_2_AEU2_Playback is shown in Figure 2-104 and described in Table 2-129.

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Figure 2-104 LED_2_AEU2_Playback Register

7	6	5	4	3	2	1	0
RESERVED						led_2_aeu2_pt
R-0h						R/W-0h

Table 2-129 LED_2_AEU2_Playback Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1-0	led_2_aeu2_pt	R/W	0h	AEU2 pattern playback times of LED_2; 0h = 0 time; 1h = 1 time; 2h = 2 times; 3h = Infinite times

2.13.19 LED_2_AEU3_PWM_1 Register (Offset = C6h) [Reset = 00h]

LED_2_AEU3_PWM_1 is shown in Figure 2-105 and described in Table 2-130.

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Figure 2-105 LED_2_AEU3_PWM_1 Register

7	6	5	4	3	2	1	0
led_2_aeu3_pwm1
R/W-0h

Table 2-130 LED_2_AEU3_PWM_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu3_pwm1	R/W	0h	AEU3_PWM1 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.20 LED_2_AEU3_PWM_2 Register (Offset = C7h) [Reset = 00h]

LED_2_AEU3_PWM_2 is shown in Figure 2-106 and described in Table 2-131.

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Figure 2-106 LED_2_AEU3_PWM_2 Register

7	6	5	4	3	2	1	0
led_2_aeu3_pwm2
R/W-0h

Table 2-131 LED_2_AEU3_PWM_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu3_pwm2	R/W	0h	AEU3_PWM2 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.21 LED_2_AEU3_PWM_3 Register (Offset = C8h) [Reset = 00h]

LED_2_AEU3_PWM_3 is shown in Figure 2-107 and described in Table 2-132.

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Figure 2-107 LED_2_AEU3_PWM_3 Register

7	6	5	4	3	2	1	0
led_2_aeu3_pwm3
R/W-0h

Table 2-132 LED_2_AEU3_PWM_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu3_pwm3	R/W	0h	AEU3_PWM3 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.22 LED_2_AEU3_PWM_4 Register (Offset = C9h) [Reset = 00h]

LED_2_AEU3_PWM_4 is shown in Figure 2-108 and described in Table 2-133.

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Figure 2-108 LED_2_AEU3_PWM_4 Register

7	6	5	4	3	2	1	0
led_2_aeu3_pwm4
R/W-0h

Table 2-133 LED_2_AEU3_PWM_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu3_pwm4	R/W	0h	AEU3_PWM4 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.23 LED_2_AEU3_PWM_5 Register (Offset = CAh) [Reset = 00h]

LED_2_AEU3_PWM_5 is shown in Figure 2-109 and described in Table 2-134.

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Figure 2-109 LED_2_AEU3_PWM_5 Register

7	6	5	4	3	2	1	0
led_2_aeu3_pwm5
R/W-0h

Table 2-134 LED_2_AEU3_PWM_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	led_2_aeu3_pwm5	R/W	0h	AEU3_PWM5 setting of LED_2; 0h = 0; 1h = 0.39%; 2h = 0.78%; ... 80h = 50.2%; ... FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.13.24 LED_2_AEU3_T12 Register (Offset = CBh) [Reset = 00h]

LED_2_AEU3_T12 is shown in Figure 2-110 and described in Table 2-135.

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Figure 2-110 LED_2_AEU3_T12 Register

7	6	5	4	3	2	1	0
led_2_aeu3_t2				led_2_aeu3_t1
R/W-0h				R/W-0h

Table 2-135 LED_2_AEU3_T12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	led_2_aeu3_t2	R/W	0h	AEU3_T2 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;
3-0	led_2_aeu3_t1	R/W	0h	AEU3_T1 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;

2.13.25 LED_2_AEU3_T34 Register (Offset = CCh) [Reset = 00h]

LED_2_AEU3_T34 is shown in Figure 2-111 and described in Table 2-136.

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Figure 2-111 LED_2_AEU3_T34 Register

7	6	5	4	3	2	1	0
led_2_aeu3_t4				led_2_aeu3_t3
R/W-0h				R/W-0h

Table 2-136 LED_2_AEU3_T34 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	led_2_aeu3_t4	R/W	0h	AEU3_T4 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;
3-0	led_2_aeu3_t3	R/W	0h	AEU3_T3 slope time setting of LED_2; 0h = no pause time; 1h = 0.09s; 2h = 0.18s; 3h = 0.36s; 4h = 0.54s; 5h = 0.80s; 6h = 1.07s; 7h = 1.52s; 8h = 2.06s; 9h = 2.50s; Ah = 3.04s; Bh = 4.02s; Ch = 5.01s; Dh = 5.99s; Eh = 7.06s; Fh = 8.05s;

2.13.26 LED_2_AEU3_Playback Register (Offset = CDh) [Reset = 00h]

LED_2_AEU3_Playback is shown in Figure 2-112 and described in Table 2-137.

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Figure 2-112 LED_2_AEU3_Playback Register

7	6	5	4	3	2	1	0
RESERVED						led_2_aeu3_pt
R-0h						R/W-0h

Table 2-137 LED_2_AEU3_Playback Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1-0	led_2_aeu3_pt	R/W	0h	AEU3 pattern playback times of LED_2; 0h = 0 time; 1h = 1 time; 2h = 2 times; 3h = Infinite times