SNVU926 October   2024 LP5810

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1Introduction/Feature Overview
    1. 1.1 Overview
  4. 2 Register Maps
    1. 2.1  Register Map Table
    2. 2.2  Device_Enable Registers
    3. 2.3  Config Registers
    4. 2.4  Command Registers
    5. 2.5  LED_Enable Registers
    6. 2.6  Fault_Clear Registers
    7. 2.7  Reset Registers
    8. 2.8  Manual_DC Registers
    9. 2.9  Manual_PWM Registers
    10. 2.10 Autonomous_DC Registers
    11. 2.11 LED_0_Autonomous_Animation Registers
    12. 2.12 LED_1_Autonomous_Animation Registers
    13. 2.13 LED_2_Autonomous_Animation Registers
    14. 2.14 LED_3_Autonomous_Animation Registers
    15. 2.15 Flag Registers
  5.   Revision History

2.15 Flag Registers

Table 2-166 lists the memory-mapped registers for the Flag registers. All register offset addresses not listed in Table 2-166 should be considered as reserved locations and the register contents should not be modified.

Table 2-166 FLAG Registers
OffsetAcronymRegister NameSection
300hTSD_Config_StatusConfiguration fault and TSD flagsGo
301hLOD_Status_0LOD flags of LED_0 to LED_3Go
302hLOD_Status_1Reserved
303hLSD_Status_0LSD flags of LED_0 to LED_3Go
304hLSD_Status_1Reserved
305hAuto_PWM_0PWM value in autonomous mode of LED_0Go
306hAuto_PWM_1PWM value in autonomous mode of LED_1Go
307hAuto_PWM_2PWM value in autonomous mode of LED_2Go
308hAuto_PWM_3PWM value in autonomous mode of LED_3Go
315hAEP_Status_0Autonomous engine pattern status of LED_0 and LED_1Go
316hAEP_Status_1Autonomous engine pattern status of LED_2 and LED_3Go

Complex bit access types are encoded to fit into small table cells. Table 2-167 shows the codes that are used for access types in this section.

Table 2-167 Flag Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

2.15.1 TSD_Config_Status Register (Offset = 300h) [Reset = 00h]

TSD_Config_Status is shown in Figure 2-139 and described in Table 2-168.

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Figure 2-139 TSD_Config_Status Register
76543210
RESERVEDtsd_statusconfig_err_status
R-0hR-0hR-0h
Table 2-168 TSD_Config_Status Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0h Reserved
1tsd_statusR0h Boost/Linear TSD fault flag; 0h = Boost/Linear TSD are not detected; 1h = Boost/Linear TSD are detected
0config_err_statusR0h Configuration fault flag; 0h = LED_CONFIG and SCAN_ORDERx registers are properly set; 1h = LED_CONFIG and SCAN_ORDERx registers are improperly set

2.15.2 LOD_Status_0 Register (Offset = 301h) [Reset = 00h]

LOD_Status_0 is shown in Figure 2-140 and described in Table 2-169.

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Figure 2-140 LOD_Status_0 Register
76543210
RESERVEDlod_status_3lod_status_2lod_status_1lod_status_0
R-0hR-0hR-0hR-0hR-0h
Table 2-169 LOD_Status_0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3lod_status_3R0h LED_3 LOD status flag; 0h = LOD fault is not detected; 1h = LOD fault is detected
2lod_status_2R0h LED_2 LOD status flag; 0h = LOD fault is not detected; 1h = LOD fault is detected
1lod_status_1R0h LED_1 LOD status flag; 0h = LOD fault is not detected; 1h = LOD fault is detected
0lod_status_0R0h LED_0 LOD status flag; 0h = LOD fault is not detected; 1h = LOD fault is detected

2.15.3 LOD_Status_1 Register (Offset = 302h) [Reset = 00h]

LOD_Status_1 is shown in Figure 2-141 and described in Table 2-170.

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Figure 2-141 LOD_Status_1 Register
76543210
RESERVED
R-0h
Table 2-170 LOD_Status_1 Register Field Descriptions
BitFieldTypeResetDescription
7-0RESERVEDR0h Reserved

2.15.4 LSD_Status_0 Register (Offset = 303h) [Reset = 00h]

LSD_Status_0 is shown in Figure 2-142 and described in Table 2-171.

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Figure 2-142 LSD_Status_0 Register
76543210
RESERVEDlsd_status_3lsd_status_2lsd_status_1lsd_status_0
R-0hR-0hR-0hR-0hR-0h
Table 2-171 LSD_Status_0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3lsd_status_3R0h LED_3 LSD status flag; 0h = LSD fault is not detected; 1h = LSD fault is detected
2lsd_status_2R0h LED_2 LSD status flag; 0h = LSD fault is not detected; 1h = LSD fault is detected
1lsd_status_1R0h LED_1 LSD status flag; 0h = LSD fault is not detected; 1h = LSD fault is detected
0lsd_status_0R0h LED_0 LSD status flag; 0h = LSD fault is not detected; 1h = LSD fault is detected

2.15.5 LSD_Status_1 Register (Offset = 304h) [Reset = 00h]

LSD_Status_1 is shown in Figure 2-143 and described in Table 2-172.

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Figure 2-143 LSD_Status_1 Register
76543210
RESERVED
R-0h
Table 2-172 LSD_Status_1 Register Field Descriptions
BitFieldTypeResetDescription
7-0RESERVEDR0h Reserved

2.15.6 Auto_PWM_0 Register (Offset = 305h) [Reset = 00h]

Auto_PWM_0 is shown in Figure 2-144 and described in Table 2-173.

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Figure 2-144 Auto_PWM_0 Register
76543210
pwm_auto_0
R-0h
Table 2-173 Auto_PWM_0 Register Field Descriptions
BitFieldTypeResetDescription
7-0pwm_auto_0R0h PWM value in autonomous mode of LED_0, precise when pause the animation

2.15.7 Auto_PWM_1 Register (Offset = 306h) [Reset = 00h]

Auto_PWM_1 is shown in Figure 2-145 and described in Table 2-174.

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Figure 2-145 Auto_PWM_1 Register
76543210
pwm_auto_1
R-0h
Table 2-174 Auto_PWM_1 Register Field Descriptions
BitFieldTypeResetDescription
7-0pwm_auto_1R0h PWM value in autonomous mode of LED_1, precise when pause the animation

2.15.8 Auto_PWM_2 Register (Offset = 307h) [Reset = 00h]

Auto_PWM_2 is shown in Figure 2-146 and described in Table 2-175.

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Figure 2-146 Auto_PWM_2 Register
76543210
pwm_auto_2
R-0h
Table 2-175 Auto_PWM_2 Register Field Descriptions
BitFieldTypeResetDescription
7-0pwm_auto_2R0h PWM value in autonomous mode of LED_2, precise when pause the animation

2.15.9 Auto_PWM_3 Register (Offset = 308h) [Reset = 00h]

Auto_PWM_3 is shown in Figure 2-147 and described in Table 2-176.

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Figure 2-147 Auto_PWM_3 Register
76543210
pwm_auto_3
R-0h
Table 2-176 Auto_PWM_3 Register Field Descriptions
BitFieldTypeResetDescription
7-0pwm_auto_3R0h PWM value in autonomous mode of LED_3, precise when pause the animation

2.15.10 AEP_Status_0 Register (Offset = 315h) [Reset = 3Fh]

AEP_Status_0 is shown in Figure 2-148 and described in Table 2-177.

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Figure 2-148 AEP_Status_0 Register
76543210
RESERVEDaep_status_1aep_status_0
R-0hR-7hR-7h
Table 2-177 AEP_Status_0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-3aep_status_1R7h Autonomous engine pattern status of LED_1; 0h = During APU1; 1h = During AEU1; 2h = During AEU2; 3h = During AEU3; 4h = During APU2; 5/6/7h = Error
2-0aep_status_0R7h Autonomous engine pattern status of LED_0; 0h = During APU1; 1h = During AEU1; 2h = During AEU2; 3h = During AEU3; 4h = During APU2; 5/6/7h = Error

2.15.11 AEP_Status_1 Register (Offset = 316h) [Reset = 3Fh]

AEP_Status_1 is shown in Figure 2-149 and described in Table 2-178.

Return to the Summary Table.

Figure 2-149 AEP_Status_1 Register
76543210
RESERVEDaep_status_3aep_status_2
R-0hR-7hR-7h
Table 2-178 AEP_Status_1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-3aep_status_3R7h Autonomous engine pattern status of LED_3; 0h = During APU1; 1h = During AEU1; 2h = During AEU2; 3h = During AEU3; 4h = During APU2; 5/6/7h = Error
2-0aep_status_2R7h Autonomous engine pattern status of LED_2; 0h = During APU1; 1h = During AEU1; 2h = During AEU2; 3h = During AEU3; 4h = During APU2; 5/6/7h = Error