SNVSB23
March 2018
LP87521-Q1
,
LP87522-Q1
,
LP87523-Q1
,
LP87524-Q1
,
LP87525-Q1
PRODUCTION DATA.
1
Features
2
Applications
Simplified Schematic
3
Description
Efficiency vs Output Current
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
I2C Serial Bus Timing Requirements
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Descriptions
8.3.1
Multi-Phase DC/DC Converters
8.3.1.1
Overview
8.3.1.2
Multiphase Operation, Phase Adding, and Phase-Shedding
8.3.1.3
Transition Between PWM and PFM Modes
8.3.1.4
Multiphase Switcher Configurations
8.3.1.5
Buck Converter Load-Current Measurement
8.3.1.6
Spread-Spectrum Mode
8.3.2
Sync Clock Functionality
8.3.3
Power-Up
8.3.4
Regulator Control
8.3.4.1
Enabling and Disabling Regulators
8.3.4.2
Changing Output Voltage
8.3.5
Enable and Disable Sequences
8.3.6
Device Reset Scenarios
8.3.7
Diagnosis and Protection Features
8.3.7.1
Power-Good Information (PGOOD Pin)
8.3.7.2
Warnings for Diagnosis (Interrupt)
8.3.7.2.1
Output Power Limit
8.3.7.2.2
Thermal Warning
8.3.7.3
Protection (Regulator Disable)
8.3.7.3.1
Short-Circuit and Overload Protection
8.3.7.3.2
Overvoltage Protection
8.3.7.3.3
Thermal Shutdown
8.3.7.4
Fault (Power Down)
8.3.7.4.1
Undervoltage Lockout
8.3.8
GPIO Signal Operation
8.3.9
Digital Signal Filtering
8.4
Device Functional Modes
8.4.1
Modes of Operation
8.5
Programming
8.5.1
I2C-Compatible Interface
8.5.1.1
Data Validity
8.5.1.2
Start and Stop Conditions
8.5.1.3
Transferring Data
8.5.1.4
I2C-Compatible Chip Address
8.5.1.5
Auto-Increment Feature
8.6
Register Maps
8.6.1
Register Descriptions
8.6.1.1
OTP_REV
8.6.1.2
BUCK0_CTRL1
8.6.1.3
BUCK1_CTRL1
8.6.1.4
BUCK2_CTRL1
8.6.1.5
BUCK3_CTRL1
8.6.1.6
BUCK0_VOUT
8.6.1.7
BUCK0_FLOOR_VOUT
8.6.1.8
BUCK1_VOUT
8.6.1.9
BUCK1_FLOOR_VOUT
8.6.1.10
BUCK2_VOUT
8.6.1.11
BUCK2_FLOOR_VOUT
8.6.1.12
BUCK3_VOUT
8.6.1.13
BUCK3_FLOOR_VOUT
8.6.1.14
BUCK0_DELAY
8.6.1.15
BUCK1_DELAY
8.6.1.16
BUCK2_DELAY
8.6.1.17
BUCK3_DELAY
8.6.1.18
GPIO2_DELAY
8.6.1.19
GPIO3_DELAY
8.6.1.20
RESET
8.6.1.21
CONFIG
8.6.1.22
INT_TOP1
8.6.1.23
INT_TOP2
8.6.1.24
INT_BUCK_0_1
8.6.1.25
INT_BUCK_2_3
8.6.1.26
TOP_STAT
8.6.1.27
BUCK_0_1_STAT
8.6.1.28
BUCK_2_3_STAT
8.6.1.29
TOP_MASK1
8.6.1.30
TOP_MASK2
8.6.1.31
BUCK_0_1_MASK
8.6.1.32
BUCK_2_3_MASK
8.6.1.33
SEL_I_LOAD
8.6.1.34
I_LOAD_2
8.6.1.35
I_LOAD_1
8.6.1.36
PGOOD_CTRL1
8.6.1.37
PGOOD_CTRL2
8.6.1.38
PGOOD_FLT
8.6.1.39
PLL_CTRL
8.6.1.40
PIN_FUNCTION
8.6.1.41
GPIO_CONFIG
8.6.1.42
GPIO_IN
8.6.1.43
GPIO_OUT
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Design Requirements
9.2.1.1
Inductor Selection
9.2.1.2
Input Capacitor Selection
9.2.1.3
Output Capacitor Selection
9.2.1.4
Snubber Components
9.2.1.5
Supply Filtering Components
9.2.1.6
Current Limit vs. Maximum Output Current
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Related Links
12.4
Receiving Notification of Documentation Updates
12.5
Community Resources
12.6
Trademarks
12.7
Electrostatic Discharge Caution
12.8
Glossary
13
Mechanical, Packaging, and Orderable Information
8.3.4
Regulator Control