SNAS407H Data sheet | 德州仪器 TI.com.cn

SNAS407H August 2007 – April 2015 DAC128S085

PRODUCTION DATA.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽¹⁾

	MIN	MAX	UNIT
Supply Voltage, V_A		6.5	V
Voltage on any Input Pin	−0.3	6.5	V
Input Current at Any Pin⁽²⁾		10	mA
Package Input Current⁽²⁾		30	mA
Power Consumption at T_A = 25°C		See ⁽³⁾
Junction Temperature		150	°C
Storage Temperature, T_stg	−65	150	°C

(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

(2) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 30-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to three.

(3) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by T_Jmax, the junction-to-ambient thermal resistance (R_θJA), and the ambient temperature (T_A), and can be calculated using the formula P_DMAX = (T_Jmax − T_A) / R_θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (for example, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed). Such conditions should always be avoided.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000
		Machine Model	±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Operating Temperature Range		−40 ≤ T_A ≤ +125	°C
Supply Voltage, V_A	2.7	5.5	V
Reference Voltage, V_REF1,2	0.5	V_A	V
Digital Input Voltage⁽¹⁾	0.0	5.5	V
Output Load	0	1500	pF
SCLK Frequency		40	MHz

(1) The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of V_A, will not cause errors in the conversion result. For example, if V_A is 3 V, the digital input pins can be driven with a 5-V logic device.
DAC128S085 30016904.gif

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		DAC128S085		UNIT
		PW (TSSOP)	RGH (WQFN)
		16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	98	34	°C/W
R_θJA	Junction-to-ambient thermal resistance	31	25
R_θJA	Junction-to-ambient thermal resistance	43	11
φ_JT	Junction-to-top characterization parameter	2	0.2
φ_JB	Junction-to-board characterization parameter	43	11

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

The following specifications apply for V_A = 2.7 V to 5.5 V, V_REF1 = V_REF2 = V_A, C_L = 200 pF to GND, f_SCLK = 30 MHz, input code range 48 to 4047. All limits are at T_A = 25°C, unless otherwise specified.

	PARAMETER	TEST CONDITIONS		MIN⁽²⁾	TYP	MAX⁽²⁾	UNIT
STATIC PERFORMANCE
	Resolution	T_MIN ≤ T_A ≤ T_MAX		12			Bits
	Monotonicity	T_MIN ≤ T_A ≤ T_MAX		12			Bits
INL	Integral Non-Linearity				±2		LSB
INL	Integral Non-Linearity	T_MIN ≤ T_A ≤ T_MAX				±8	LSB
DNL	Differential Non-Linearity				0.15		LSB
		T_MIN ≤ T_A ≤ T_MAX				0.75	LSB
					−0.09		LSB
		T_MIN ≤ T_A ≤ T_MAX		−0.4			LSB
ZE	Zero Code Error	I_OUT = 0			+5		mV
ZE	Zero Code Error	T_MIN ≤ T_A ≤ T_MAX				15	mV
FSE	Full-Scale Error	I_OUT = 0			−0.1%		FSR
FSE	Full-Scale Error	T_MIN ≤ T_A ≤ T_MAX				−0.75%	FSR
GE	Gain Error				−0.2%		FSR
GE	Gain Error	T_MIN ≤ T_A ≤ T_MAX				−1 %	FSR
ZCED	Zero Code Error Drift				−20		µV/°C
TC GE	Gain Error Tempco				−1		ppm/°C
OUTPUT CHARACTERISTICS
	Output Voltage Range	T_MIN ≤ T_A ≤ T_MAX		0		V_REF1,2	V
I_OZ	High-Impedance Output Leakage Current⁽³⁾	T_MIN ≤ T_A ≤ T_MAX				±1	µA
ZCO	Zero Code Output	V_A = 3 V, I_OUT = 200 µA			10		mV
		V_A = 3 V, I_OUT = 1 mA			45		mV
		V_A = 5 V, I_OUT = 200 µA			8		mV
		V_A = 5 V, I_OUT = 1 mA			34		mV
FSO	Full Scale Output	V_A = 3 V, I_OUT = 200 µA			2.984		V
		V_A = 3 V, I_OUT = 1 mA			2.933		V
		V_A = 5 V, I_OUT = 200 µA			4.987		V
		V_A = 5 V, I_OUT = 1 mA			4.955		V
I_OS	Output Short Circuit Current (source)⁽⁴⁾	V_A = 3 V, V_OUT = 0 V, Input Code = FFFh			−50		mA
I_OS	Output Short Circuit Current (source)⁽⁴⁾	V_A = 5 V, V_OUT = 0 V, Input Code = FFFh			−60		mA
I_OS	Output Short Circuit Current (sink)⁽⁴⁾	V_A = 3 V, V_OUT = 3 V, Input Code = 000h			50		mA
I_OS	Output Short Circuit Current (sink)⁽⁴⁾	V_A = 5 V, V_OUT = 5 V, Input Code = 000h			70		mA
I_O	Continuous Output Current per channel⁽³⁾	T_A = 105°C T_MIN ≤ T_A ≤ T_MAX				10	mA
I_O	Continuous Output Current per channel⁽³⁾	T_A = 125°C T_MIN ≤ T_A ≤ T_MAX				6.5	mA
C_L	Maximum Load Capacitance	R_L = ∞			1500		pF
C_L	Maximum Load Capacitance	R_L = 2 kΩ			1500		pF
Z_OUT	DC Output Impedance				8		Ω
REFERENCE INPUT CHARACTERISTICS
VREF1,2	Input Range Minimum				0.5		V
	Input Range Minimum	T_MIN ≤ T_A ≤ T_MAX		2.7			V
	Input Range Maximum	T_MIN ≤ T_A ≤ T_MAX				V_A	V
	Input Impedance				30		kΩ
LOGIC INPUT CHARACTERISTICS
I_IN	Input Current⁽³⁾	T_MIN ≤ T_A ≤ T_MAX				±1	µA
V_IL	Input Low Voltage	V_A = 2.7 V to 3.6 V			1		V
		T_MIN ≤ T_A ≤ T_MAX				0.6	V
		V_A = 4.5 V to 5.5 V			1.1		V
						0.8	V
V_IH	Input High Voltage	V_A = 2.7 V to 3.6 V			1.4		V
		T_MIN ≤ T_A ≤ T_MAX		2.1			V
		V_A = 4.5 V to 5.5 V			2		V
		T_MIN ≤ T_A ≤ T_MAX		2.4			V
C_IN	Input Capacitance⁽³⁾	T_MIN ≤ T_A ≤ T_MAX				3	pF
POWER REQUIREMENTS
V_A	Supply Voltage Minimum	T_MIN ≤ T_A ≤ T_MAX		2.7			V
V_A	Supply Voltage Maximum	T_MIN ≤ T_A ≤ T_MAX				5.5	V
I_N	Normal Supply Current for supply pin V_A	f_SCLK = 30 MHz, output unloaded	V_A = 2.7 V to 3.6 V		460		µA
			T_MIN ≤ T_A ≤ T_MAX			560	µA
			V_A = 4.5 V to 5.5 V		650		µA
						830	µA
	Normal Supply Current for V_REF1 or V_REF2	f_SCLK = 30 MHz, output unloaded	V_A = 2.7 V to 3.6 V		95		µA
			T_MIN ≤ T_A ≤ T_MAX			130	µA
			V_A = 4.5 V to 5.5 V		160		µA
						220	µA
I_ST	Static Supply Current for supply pin V_A	f_SCLK = 0, output unloaded	V_A = 2.7 V to 3.6 V		370		µA
	Static Supply Current for supply pin V_A	f_SCLK = 0, output unloaded	V_A = 4.5 V to 5.5 V		440		µA
	Static Supply Current for V_REF1 or V_REF2	f_SCLK = 0, output unloaded	V_A = 2.7 V to 3.6 V		95		µA
	Static Supply Current for V_REF1 or V_REF2	f_SCLK = 0, output unloaded	V_A = 4.5 V to 5.5 V		160		µA
I_PD	Total Power Down Supply Current for all PD Modes ⁽³⁾	f_SCLK = 30 MHz, SYNC = V_A and D_IN = 0V after PD mode loaded	V_A = 2.7 V to 3.6 V		0.2		µA
						1.5	µA
			V_A = 4.5 V to 5.5 V		0.5		µA
			T_MIN ≤ T_A ≤ T_MAX			3	µA
		f_SCLK = 0, SYNC = V_A and D_IN = 0V after PD mode loaded	V_A = 2.7 V to 3.6 V		0.1		µA
			T_MIN ≤ T_A ≤ T_MAX			1	µA
			V_A = 4.5 V to 5.5 V		0.2		µA
			T_MIN ≤ T_A ≤ T_MAX			2	µA
P_N	Total Power Consumption (output unloaded)	f_SCLK = 30 MHz output unloaded	V_A = 2.7 V to 3.6 V		1.95		mW
			T_MIN ≤ T_A ≤ T_MAX			3	mW
			V_A = 4.5 V to 5.5 V		4.85		mW
			T_MIN ≤ T_A ≤ T_MAX			7	mW
		f_SCLK = 0 output unloaded	V_A = 2.7 V to 3.6 V		1.68		mW
		f_SCLK = 0 output unloaded	V_A = 4.5 V to 5.5 V		3.80		mW
P_PD	Total Power Consumption in all PD Modes, ⁽³⁾	f_SCLK = 30 MHz, SYNC = V_A and D_IN = 0V after PD mode loaded	V_A = 2.7 V to 3.6 V		0.6		µW
			T_MIN ≤ T_A ≤ T_MAX			5.4	µW
			V_A = 4.5V to 5.5V		2.5		µW
			T_MIN ≤ T_A ≤ T_MAX			16.5	µW
		f_SCLK = 0, SYNC = V_A and D_IN = 0V after PD mode loaded	V_A = 2.7 V to 3.6 V		0.3		µW
			T_MIN ≤ T_A ≤ T_MAX			3.6	µW
			V_A = 4.5 V to 5.5 V		1		µW
			T_MIN ≤ T_A ≤ T_MAX			11	µW

7.6 AC and Timing Characteristics

The following specifications apply for V_A = 2.7 V to 5.5 V, V_REF1,2 = V_A, C_L = 200 pF to GND, f_SCLK = 30 MHz, input code range 48 to 4047. All limits are at T_A = 25°C, unless otherwise specified.

			MIN⁽²⁾	NOM	MAX⁽²⁾	UNIT
f_SCLK	SCLK Frequency			40		MHz
f_SCLK	SCLK Frequency	T_MIN ≤ T_A ≤ T_MAX			30	MHz
t_s	Output Voltage Settling Time ⁽³⁾	400h to C00h code change R_L = 2 kΩ, C_L = 200 pF		6		µs
t_s	Output Voltage Settling Time ⁽³⁾	T_MIN ≤ T_A ≤ T_MAX			8.5	µs
SR	Output Slew Rate			1		V/µs
GI	Glitch Impulse	Code change from 800h to 7FFh		40		nV-sec
DF	Digital Feedthrough			0.5		nV-sec
DC	Digital Crosstalk			0.5		nV-sec
CROSS	DAC-to-DAC Crosstalk			1		nV-sec
MBW	Multiplying Bandwidth	V_REF1,2 = 2.5 V ± 2 Vpp		360		kHz
THD+N	Total Harmonic Distortion Plus Noise	V_REF1,2 = 2.5 V ± 0.5 Vpp 100 Hz < f_IN < 20 kHz		−80		dB
ONSD	Output Noise Spectral Density	DAC Code = 800 h, 10 kHz		40		nV/sqrt (Hz)
ON	Output Noise	BW = 30 kHz		14		µV
t_WU	Wake-Up Time	V_A = 3 V		3		µsec
t_WU	Wake-Up Time	V_A = 5 V		20		µsec
1/f_SCLK	SCLK Cycle Time. See Figure 1			25		ns
1/f_SCLK	SCLK Cycle Time. See Figure 1	T_MIN ≤ T_A ≤ T_MAX	33			ns
t_CH	SCLK High time. See Figure 1			7		ns
t_CH	SCLK High time. See Figure 1	T_MIN ≤ T_A ≤ T_MAX	10			ns
t_CL	SCLK Low Time. See Figure 1			7		ns
t_CL	SCLK Low Time. See Figure 1	T_MIN ≤ T_A ≤ T_MAX	10			ns
t_SS	SYNC Set-up Time prior to SCLK Falling Edge. See Figure 1			3	1 / f_SCLK - 3	ns
t_SS	SYNC Set-up Time prior to SCLK Falling Edge. See Figure 1	T_MIN ≤ T_A ≤ T_MAX	10			ns
t_DS	Data Set-Up Time prior to SCLK Falling Edge. See Figure 1			1		ns
t_DS	Data Set-Up Time prior to SCLK Falling Edge. See Figure 1	T_MIN ≤ T_A ≤ T_MAX	2.5			ns
t_DH	Data Hold Time after SCLK Falling Edge. See Figure 1			1		ns
t_DH	Data Hold Time after SCLK Falling Edge. See Figure 1	T_MIN ≤ T_A ≤ T_MAX	2.5			ns
t_SH	SYNC Hold Time after the 16th falling edge of SCLK. See Figure 1			0	1 / f_SCLK - 3	ns
t_SH		T_MIN ≤ T_A ≤ T_MAX	3			ns
t_SYNC	SYNC High Time. See Figure 1			5		ns
t_SYNC	SYNC High Time. See Figure 1	T_MIN ≤ T_A ≤ T_MAX	15			ns

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recomended Operating Ratings indicate conditions for which the device is functional, but do not specify specific performance limits. For ensured specifications and test conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Absolute Maximum Ratings is not recommended.

(2) Test limits are ensured to TI's AOQL (Average Outgoing Quality Level).

(3) This parameter is ensured by design and/or characterization and is not tested in production.

(4) This parameter does not represent a condition which the DAC can sustain continuously. See the continuous output current specification for the maximum DAC output current per channel.