SNAK013 November   2022 LMK04832-SEP

 

  1.   Abstract
  2.   Trademarks
  3. 1Product Description
  4. 2Test Setup
    1. 2.1 SEL Test
    2. 2.2 SEFI Test
    3. 2.3 Test Facility
  5. 3Results
    1. 3.1 SEL Results
    2. 3.2 SEFI Results
  6. 4Summary
  7. 5References

1 Product Description

The LMK04832-SEP(1) is part of TI's family of Space Enhanced Plastic products(2) released for space missions with reduced radiation and reliability requirements. The device is a JESD204B, JESD204C(3) compliant clock jitter cleaner with two PLL loops – one for jitter cleaning and one for clock generation. The LMK04832-SEP has reduced radiation performance compared to the QML-V option – LMK04832-SP along with a different pinout and electrical performance.

LMK04832-SEP is the generic part number (GPN) for the product. The flight-grade orderable part number is LMK04832MPAPSEP or V62P22612-01XE(4). A prototype, which does not receive full space-grade processing and testing, LMK04832PAP/EM, can be ordered for engineering evaluation.

Figure 1-1 shows a simplified block diagram of the LMK04832-SEP, and a more detailed block diagram is shown in Figure 1-2. The LMK04832-SEP can provide very low jitter clocking signals up to 3.2 GHz on 14 individually programmable outputs. The device can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 can operate with either internal or external VCOs(1).

Figure 1-1 LMK04832-SEP Configured in Dual-Loop Mode

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B-compliant data converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. JESD204B is a serial interface standard used between data converters and logic devices with serial data rates up to 12.5 Gbps(4). SYSREF is a timing phase reference synchronous with the output signal.

Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems. The outputs of the LMK04832-SEP can be individually configured in many different output formats: CML, LVPECL, LCPECL, HSDS, LVDS, or 2 × LVCMOS. The output frequency and delay can be individually set for each output. The product pinout is shown in Figure 1-3.

The part is configured through a serial peripheral interface (SPI) and the configuration is stored in registers. The state of the registers can be accessed through a register read. The operating voltage of the LMK04832-SEP is 3.15 V to 3.45 V.

The LMK04832-SEP is manufactured on a TI BiCMOS process with SiGe NPN bipolar transistors.

Figure 1-2 LMK04832-SEP Detailed Block Diagram
Figure 1-3 LMK04832-SEP Pinout