SLVZ025 March 2022 LP8764-Q1
Silicon Revision 2.0
When SPI interface is used, the SDO_SPI (GPIO3) slew-rate for falling edge is reduced. Serial Peripheral Interface (SPI) Electrical characteristics Pos15.10a "New output data valid after SCLK falling, VVIO = 1.8 V" is max. 72 ns (instead of max. 60 ns) and Pos15.10b "New output data valid after SCLK falling, VVIO = 3.3 V" is max. 110 ns (instead of max. 60 ns). The new output data validity after the SCK_SPI pin falling edge limits the maximum clock frequency and Pos15.2 Cycle time.
The SCK_SPI clock frequency must be selected so that Pos15.10a/b timing parameters can be tolerated by the SPI host.
Silicon Revision 2.0
Voltage monitor Analog-BIST function is performed every time when the Buck or VMONx pin voltage monitor is enabled. The Analog-BIST function may cause false over voltage or under voltage interrupt for the tested Buck or VMONx pin voltage monitor, which can generate trigger to state-machine based on the power group selection of the voltage monitor and thus cause unwanted state transition.
There are two use cases that requires software workaround:
1) When the voltage monitor for Buck regulator or VMON1/2 pin is enabled by software (I2C or SPI write), the corresponding over voltage and under voltage interrupt masking must be enabled before enabling the voltage monitor. The Analog-BIST is performed for the voltage monitor as described in Datasheet chapter "Output Voltage Monitor and PGOOD Generation". The over voltage and under voltage interrupt masking must be disabled earliest at time calculated by programmed voltage level (Vout) divided by the programmed slew-rate and by adding 500 us time.
2) When the software generates Runtime-BIST request, it must enable over voltage and under voltage interrupt masks at least for all enabled Buck and VMON1/2 voltage monitors before requesting the Runtime-BIST. The completion of the succesful Runtime-BIST is indicated by BIST_PASS_INT interrupt and after detecting the interrupt the software must disable the over voltage and under voltage interrupt masks. If the Runtime-BIST fails, the device automatically jumps to SAFE RECOVERY state and performs an automatic startup (unless recovery counter limit is exceeded). During the startup the default NVM settings are read and the over voltage and under voltage interrupt masking is cleared.
The voltage monitor enable events generated by the state-machine are fixed in the state-machine configuration by masking the over-voltage and under voltage interrupts before enabling the voltage monitor and unmasking the corresponding interrupts when the Analog-BIST is done.
Silicon Revision 2.0
If SPI interface is used and CS_SPI is low when the device is started up (VCCA is rising) and CS_SPI pin rises during mission states, SPI frame error interrupt (COMM_FRM_ERR_INT) is generated.
There is no workaroud for SPI frame error generation, but the SPI frame error only generates an interrupt (no state transition) and it can be cleared by software after startup.
Silicon Revision 2.0
After the Runtime BIST is completed, under voltage and short circuit detection comparators are gated for a time period calculated by programmed voltage (Vout) divided by programmed slew-rate, and thus do not monitor the voltage during that time.
The under voltage and short circuit detection are automatically enabled after the gating time. There is no workaround for the delayed monitoring.
Silicon Revision 2.0
PVIN pin input voltage monitor is disabled in LP_STANDBY state, which causes power stage pull-down to be activated. The pull-down circuitry causes ~3mA input current from PVIN pins. This current does not affect the device operation, but in practise the LP_STANDBY mode becomes useless because it was intended to operate with very low quiescent current consumption.
There is no workaround for the issue. STANDBY mode must be used instead of LP_STANDBY mode in the application (LP_STANDBY_SEL bit is set to 0 always).
Silicon Revision 2.0
When ESM is enabled and nERR_MCU pin is set to low, ESM_MCU_PIN_INT interrupt is generated after a deglitch time and ESM_MCU_FAIL_INT interrupt is generated after delay-1 timer. If the ESM_MCU_FAIL_INT interrupt is cleared during delay-2, the ESM_MCU_FAIL_INT interrupt is generated again after elapse of delay-2 timer (ESM_MCU_RST_INT interrupt is generated at the same time).
There is no workaround for the issue. During operation the software must clear all ESM interrupts after detecting those and getting nERR_MCU back to high state.
Silicon Revision 2.0
The frame error detection counts only SCK_SPI falling edges when CS_SPI is low. SCK_SPI signal must be low when CS_SPI signal goes low or high (start and end of communication), but this is not checked by the frame error detection. For example, additional SCK_SPI rising edge at the end of the communication is not detected as frame error.
There is no workaround for the issue.
Silicon Revision 2.0
SOFT_REBOOT bit cannot be written by I2C or SPI interface during normal operation.
There is no workaround for the issue.
Silicon Revision 2.0
EN_DRV(GPIO1) cannot be driven high if VCCA voltage is different than VIO voltage (more than 10% difference). There is leakage path from VCCA which limits the EN_DRV output high voltage. The EN_DRV(GPIO1) operates correctly when VCCA and VIO are 3.3V.
No workaround for the issue. EN_DRV(GPIO1) pin operates correctly when both VCCA and VIO are 3.3V.
Silicon Revision 2.0
During Runtime BIST and just after that the PGOOD signal is forced to inactive level if Buck voltage monitoring or external voltage monitoring (VMON1/2) is selected to control the PGOOD signal. The PGOOD signal is optional selectable function for GPIO1, GPIO6 and GPIO9.
There is software workaround that disables buck output voltage monitoring and external voltage monitoring indication to PGOOD signal during Runtime BIST and thus does not force the PGOOD pin to inactive level. Before initiating the Runtime BIST, the software must set PGOOD_SEL_BUCKx and PGOOD_SEL_VMONx bits to '0' (masked). The completion of the succesful Runtime-BIST is indicated by BIST_PASS_INT interrupt and after detecting the interrupt the software must wait the longest voltage monitoring ramp time before the software can set the original settings to the PGOOD_SEL_BUCKx and PGOOD_SEL_VMONx bits. The voltage monitoring ramp time for buck and VMON1/2 pin voltage monitoring is calculated by dividing the programmed voltage level by the programmed slew-rate and by adding 500 us time for this workaround.