SLVUDO8 March   2026 LMK6B

 

  1.   1
  2. 1Description
  3. 2Features
  4.   4
  5. 3Evaluation Module Overview
    1. 3.1 Introduction
    2. 3.2 Kit Contents
    3. 3.3 Specifications
  6. 4Implementation Results
    1. 4.1 Evaluation Setup Requirement
    2. 4.2 Setup
      1. 4.2.1 Connection Diagram
      2. 4.2.2 Power Supply
      3. 4.2.3 Clock Output
      4. 4.2.4 EVM Header Configuration
      5. 4.2.5 Configuring the Output Clock Termination
    3. 4.3 Performance Data and Results
      1. 4.3.1 Typical Measurement
  7. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layout and Layer Stack-Up
      1. 5.2.1 PCB Layer Stack-Up
      2. 5.2.2 PCB Layout
    3. 5.3 Bill of Materials (BOM)
  8. 6Additional Information
    1.     Trademarks
  9. 7Related Documentation

4.2.4 EVM Header Configuration

Table 4-2 summarizes the EVM header configurations to connect and route power to the VDD domains of the individual devices, in addition to the individual output enable (OE), standby (ST), or frequency select (FSEL) pins depending on the device populated.

Table 4-2 EVM Header Configurations
ComponentNameDescription
J7,J8VDD

VDD Supply Voltage Source

J7: Tie pins 3-4 (default)

J8: Tie pins 1-2 (default)

By default, VDD is sourced from USB power supply and onboard LDO.

See Table 4-1 for more details

J10VDD_Reg

VDD_Reg Voltage Level

Tie pins 3-4 (default): Selects VDD = 3.3V

Tie pins 1-2: Selects VDD = 2.5V

J2, J4, J9Oscillator pin 1 and 2 (OE and FSEL)

Oscillator Pin 1 (OE)

Tie pins 1-3 (default): Pull LMK6B OE to VDD, clock output is enabled

Tie pins 3-5: Pull LMK6B OE to GND, clock output is disabled

Oscillator Pin 2 (FSEL)

Tie pins 2-4 (default): Pull LMK6B FSEL to VDD, output frequency = 312.5MHz

Tie pins 4-6: Pull LMK6B FSEL to GND, output frequency = 156.25MHz

Jumper removed: LMK6B FSEL is internally biased to mid-level, output frequency = 625MHz