SLVUD09 January   2025 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521910 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config
  7. 4Revision History

2.1 TPS6521910 Sequence and Power Block Diagram

TPS6521910 Example Power Block DiagramFigure 2-1 TPS6521910 Example Power Block Diagram
TPS6521910 Digital connections to AM67Figure 2-2 TPS6521910 Digital connections to AM67
Note:
  • PMIC digital signals that require external pull-up resistors: nRSTOUT, nINT, GPIO, GPO1, VSEL(to set the LDO1 start up voltage as 3.3V), MODE/STBY (to define the Bucks switching operation), I2C pins (SCL/SDA).
TPS6521910 Power-Up SequenceFigure 2-3 TPS6521910 Power-Up Sequence
TPS6521910 Power-Down SequenceFigure 2-4 TPS6521910 Power-Down Sequence