SLVUCM3A July   2023  – June 2026 AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6. 1System Description
  7. 2Device Versions
  8. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  9. 4Supporting Functional Safety ASIL-B Requirements
    1. 4.1 Additional Safety Features
  10. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  11. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  12. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  13. 8Design and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Support Resources
    3. 8.3 Trademarks
  14. 9Revision History

5 Static NVM Settings

The TPS6593-Q1 PMIC consist of user register space and an NVM. The settings in NVM, which are loaded into the user registers during the transition from INIT to BOOT BIST, are provided in this section. Note: The user registers can be changed during state transitions, such as moving from STANDBY to ACTIVE mode. The user register map is described in the TPS6593-Q1 Datasheet.