SLVUCK6 September   2022 TPS568231

 

  1.   TPS568231EVM 8-A, Regulator Evaluation Module
  2.   Trademarks
  3. 1Introduction
  4. 2Performance Specification Summary
  5. 3Modifications
    1. 3.1 Output Voltage Setpoint
    2. 3.2 Adjustable UVLO
  6. 4Test Setup and Results
    1. 4.1 Input and Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Start-Up
    4. 4.4 Shutdown
    5. 4.5 Output Voltage Ripple
  7. 5Board Layout
    1. 5.1 Layout
  8. 6Board Profile, Schematic, and List of Materials
    1. 6.1 Board Profile
    2. 6.2 Schematic
    3. 6.3 List of Materials
  9. 7References

5.1 Layout

The board layout for the TPS568231EVM is shown in Figure 5-1 to Figure 5-5. The TPS568231EVM is with four layers. The top layer contains the main power traces for VIN, VOUT, SW, and GND. Also, on the top layer are connections for the pins of the TPS568231 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors are located as close to the VIN pins and PGND pins of the IC as possible. The internal layer-1 is dedicated ground plane. The internal layer-2 contains an additional large ground copper area as well as an additional VIN and VOUT copper fill. The bottom layer is a ground plane along with 4 traces for VIN, VOUT, EN, and BOOT connection.

Figure 5-1 Top Assembly
Figure 5-2 Top Layer
Figure 5-3 Inner1 Layer
Figure 5-4 Inner2 Layer
Figure 5-5 Bottom Layer