SLVUC68 September   2021 TPSM5601R5H

 

  1.   Trademarks
  2. 1EVM Setup
  3. 2EVM Connectors and Test Points
  4. 3EVM Parameters
    1. 3.1 Maximum Output Current
    2. 3.2 Maximum VIN and VOUT Configurations
    3. 3.3 Switching Node Behavior
  5. 4Typical Performance
    1. 4.1 Typical Characteristics (VIN = 12 V)
    2. 4.2 Typical Characteristics (VIN = 24 V)
    3. 4.3 Typical Characteristics (VIN = 36 V)
    4. 4.4 Typical Characteristics (VIN = 48 V)
  6. 5Feature Description
    1. 5.1 Enable Pin (EN)
    2. 5.2 Power-Good Pin (PGOOD)
    3. 5.3 System Loop Stability
  7. 6Layout
    1. 6.1 PCB Layout
  8. 7Schematic
  9. 8Bill of Materials (BOM)
  10.   Device Support
    1.     Related Documentation
    2. 9.1 Support Resources

5.3 System Loop Stability

Stability is an important factor in power converters. The guideline for a stable design is a phase margin of at least 45°. With that in mind, the TPSM5601R5H-IBB-EVM is designed to accommodate a wide range of operating conditions with a phase margin greater than 45°. Note that the stability of the system (EVM) will be affected by the operating conditions, input voltage, and total output capacitance. Figure 5-6 demonstrates the recommended operating range for a stable design (≥ 45°). If the operating conditions are outside the recommended range, it is important to run a bode plot to ensure stability.

Figure 5-6 Recommended Operating Range for ≥ 45° Phase Margin

Table 5-1 shows the phase margin across various input voltages with a fixed –5-V output. The results measured are from the original BOM (COUT = 2 × 47 μF) of the TPSM5601R5H-IBB-EVM.

Table 5-1 Stability Analysis of TPSM5601R5H-IBB-EVM
VIN (V) VOUT (V) Max IOUT (A) Fcrossover (kHz) PHASE MARGIN (°)
12 –5 0.982 18.00 45.0
24 –5 1.184 23.30 50.8
28 –5 1.221 24.32 51.7
36 –5 1.271 26.00 53.2
48 –5 1.315 27.40 54.3