SLVUBZ8 July   2021 TPS7H5001-SP

 

  1.   1
  2.   2
    1.     3
    2.     4
  3.   5
  4.   6
  5.   7
  6.   8
  7.   9

3 EVM Connectors and Test Points

Table 3-1 is a list of major connections on the board. For further information see the relevant section in the TPS7H5001-SP Radiation-Hardness-Assured Si and GaN Dual Output Controller data sheet.

Table 3-1 EVM Board Connections
Test PointConnectionDescription
TP1, J1OUTAConnected to the gate driver in the design. Components R5, C5 can be used to test different R/C loads.
TP2, J2OUTBConnected to the gate driver in the design. Components R6, C6 can be used to test different R/C loads.
TP3, J3SRAConnected to the gate driver in the design. Components R7, C7 can be used to test different R/C loads.
TP4, J4SRBConnected to the gate driver in the design. Components R8, C8 can be used to test different R/C loads.
TP5, TP6CS_LIMInput for current sense in the design. The CS_LIM circuit provides small triangle waveform from OUTA, OUTB. Note that this can load OUTA, OUTB causing a slow in the slew rate. If R9 and R10 are unpopulated, CS_LIM can be force from TP5.
TP7VINVoltage input for the TPS7H5001-SP device
TP8ENEnable pin for the TPS7H5001-SP device, currently pulled high to VLDO
TP9COMPError amplifier output for the TPS7H5001-SP, forcing this voltage runs the TPS7H5001-SP in open loop.
TP10REFCAPInternal reference for TPS7H5001-SP
TP11, TP12SSIn a closed loop design, this slowly increases converter output voltage during start-up
TP13, TP15SYNCInputting a clock on this pin synchronizes the TPS7H5001-SP to a frequency half of the input frequency
TP14VLDOInternal voltage rail for device logic
TP20VSENSEVoltage sense for the TPS7H5001-SP. Connected to converter output voltage in the full design.
TP21RSCSlope compensation selection resistor. Sets slope compensation slew rate internal to the device.
TP22HICCConfigurability for the hiccup time of the converter. While grounded through a resistor on the EVM, in a full design it is generally a capacitor.
TP23FAULTA signal high on this node turns the TPS7H5001-SP off for any fault condition needed
TP24SPConfigurability for the delay between the synchronous rectifiers and main output
TP25RTFrequency select for the TPS7H5001-SP. Change this to vary the frequency of the converter.
TP26PSConfigurability for the delay between the main output and synchronous rectifiers
TP27LEBConfigurability for the leading edge blanking time of the converter

Table 3-2 describes and lists the connections and configuration for J6. Use J6 to switch between different DCL connections to test different duty cycle limits. Pin 1 is noted by the dot next to the pin.

Table 3-2 J6 Connections and Configuration
Pin ConnectionDuty Cycle Limit Configuration Description
Pin 1 and Pin 2100%DCL is connected high to VLDO
Pin 2 and Pin 350%DCL is connected low to AVSS
Floating75%DCL is left floating