SLVUA33A March   2014  – July 2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Slow-Start Time
      3. 1.3.3 Adjustable UVLO
  3. 2Test Setup and Results
    1. 2.1 Input/Output Connections
    2. 2.2 Efficiency
    3. 2.3 Output Voltage Load Regulation
    4. 2.4 Output Voltage Line Regulation
    5. 2.5 Load Transients
    6. 2.6 Loop Characteristics
    7. 2.7 Output Voltage Ripple
    8. 2.8 Powering Up
    9. 2.9 Shutting Down
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 Reference
  6. 5Revision History

2.1 Input/Output Connections

The TPS563900EVM-574 is provided with input/output connectors and test points as shown in Table 2-1. A power supply capable of supplying 5 A must be connected to J1 through a pair of 20-AWG wires. The loads must be connected to J3 and J4 through a pair of 20-AWG wires. The maximum load current capability is 3.5 A for each output. Wire lengths must be minimized to reduce losses in the wires. Test-point TP1 provides a place to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP11 is used to monitor VOUT1 with TP12 as the ground reference. TP15 is used to monitor VOUT2 with TP15 as the ground reference.

Table 2-1 EVM Connectors and Test Points
Reference DesignatorFunction
J1VIN input voltage connector. (See Table 1-1 for VIN range.)
J2I2C interface connector.
J3VOUT1, 1.0 V at 3.5 A maximum
J4VOUT2, 1.1 V at 3.5 A maximum
JP1MODE select. Cover JP1-2 and JP1-3 to select forced CCM mode. Leave open to select PSM pulse skipping mode for increased light-load efficiency
JP2ADDR select. Normally cover JP2-2 and JP2-3.
JP3Jumper to select internal LDO as I2C pull up voltage. Normally open to allow pull up voltage from the USB interface adapter.
JP42-pin header for VOUT1 enable. Connect EN to ground to disable, open to enable.
JP52-pin header for VOUT2 enable. Connect EN to ground to disable, open to enable.
TP1VIN test point at VIN connector.
TP2GND test point at VIN connector.
TP3LDO output test point.
TP4External I2C pull up voltage test point.
TP5VOUT1 enable test point.
TP6VOUT2 enable test point.
TP7VOUT1 slow start test point.
TP8VOUT2 slow start test point.
TP9VOUT1 LX1 switching node test point.
TP10Test point in VOUT1 voltage divider network. Used for loop response measurements when output voltage is set using external resistor divider network.
TP11Output voltage test point at VOUT1 connector.
TP12GND test point at VOUT1 connector.
TP13VOUT2 LX2 switching node test point.
TP14Test point in VOUT2 voltage divider network. Used for loop response measurements when output voltage is set using external resistor divider network.
TP15Output voltage test point at VOUT2 connector.
TP16GND test point at VOUT2 connector.
TP17Analog GND test point.
TP18I2C SDA test point.
TP19I2C SCL test point.