SLVK146 august 2023 TPS7H2211-SEP
PRODUCTION DATA
The primary concern of interest for the TPS7H2211-SEP is the robustness against the Destructive Single-Event Effects (DSEE) named as:
In mixed technologies, such as the Linear BiCMOS 7 process used on the TPS7H2211-SEP, the CMOS circuitry introduces a potential for SEL susceptibility. SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1, 2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current). This current between power and ground persists or is latched until power is removed, the device is reset, or until the device is destroyed by the high-current state. The TPS7H2211-SEP was tested for SEL at the maximum recommended voltage of 14 V and maximum load current of 3.5 A. The device exhibits no-SEL with heavy-ions of LETEFF = 48 MeV·cm2/mg at Flux ≈ 105 ions/cm2·s, fluences of ≈ 107 ions/cm2, and a die temperature of 125°C, using 109Ag.
DMOS are susceptible to SEB/SEGR while in the off state. However, the device was also evaluated on all possible cases (Enable and Disable). SEB is similar to the SEL and occurs when the parasitic BJT of the DMOSFET is turned on by the heavy ion strike. When a heavy ion with sufficient energy hits the p body, it creates an excess charge inducing a voltage drop. This voltage drop forward biases the emitter-base junction of the parasitic NPN (formed by the N+ source, the P base region, and the N-drift region). If this happens when the DMOSFET is under a high drain bias, a secondary breakdown of the parasitic npn BJT can occur, creating permanent damage of the DMOS.
When the heavy-ion hits the neck region of the DMOS (under the gate), the heavy-ion creates electron hole-pairs on the oxide and silicon. Drift separates the excess electrons and holes due to the positive bias field on the drain to source of the DMOS. Holes are driven upward to the dioxide while the electrons are transported toward the drain. The collected holes on the dioxide create an equal image of electrons on the opposite side of the gate dioxide. Since the charge injection and collection after an event is faster than the transport and recombination of the e-h pairs, a voltage transient can be developed across the gate oxide. If this build-up voltage is higher than the oxide breakdown, permanent damage can be induced on the oxide, creating a destructive gate rupture [3, 4]. The TPS7H2211-SEP was evaluated for SEB/SEGR at full load conditions (3.5 A), enabled and disabled modes and LETEFF of 48 MeV·cm2/mg using 109Ag (at angle of incidence of 0°). A flux of ≈105 ions/cm2·s, fluence of ≈107 ions/cm2, and a die temperature of ≈ 25°C per run was used during the SEB/SEGR characterization. The device is SEB/SEGR-free up to 14 V.
The TPS7H2211-SP was characterized for SET at flux of ≈ 105 ions/cm2·s, fluences of ≈ 107ions/cm2, and room temperature. The device was characterized at input voltages ranging from 4.5 V (minimum recommended voltage) to 14 V (maximum recommended voltage), at ILOAD of 3.5 A and under no-load conditions. The TPS7H2211-SP is SET-free. For more details, see the Single-Event Transients (SET) section.