SLUUDI1 December   2025 LMK3H2108

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2LMK3H2108 Configuration Summary
    1. 2.1  LMK3H2108A01
    2. 2.2  LMK3H2108A03
    3. 2.3  LMK3H2108A04
    4. 2.4  LMK3H2108A05
    5. 2.5  LMK3H2108A06
    6. 2.6  LMK3H2108A07
    7. 2.7  LMK3H2108A0D
    8. 2.8  LMK3H2108A0E
    9. 2.9  LMK3H2108A0F
    10. 2.10 LMK3H2108A11
    11. 2.11 LMK3H2108A14
    12. 2.12 LMK3H2108A15
    13. 2.13 LMK3H2108A16
    14. 2.14 LMK3H2108A17
    15. 2.15 LMK3H2108A18
  6. 3Revision History

2.14 LMK3H2108A17

LMK3H2108A17 Configuration Guide

LMK3H2108A17 Register Map

Table 2-14 LMK3H2108A17 Configuration Summary
OTP Page OUT0 Configuration OUT1 Configuration OUT2 Configuration OUT3 Configuration OUT4 Configuration OUT5 Configuration OUT6 Configuration OUT7 Configuration
Page 0 100MHz 85Ω LP-HCSL 100MHz LVCMOS P Disabled 100MHz 85Ω LP-HCSL Disabled 100MHz LVCMOS P 100MHz 85Ω LP-HCSL Disabled
Page 1 100MHz 85Ω LP-HCSL -0.5% down-spread SSC 100MHz LVCMOS P -0.5% down-spread SSC Disabled 100MHz 85Ω LP-HCSL -0.5% down-spread SSC Disabled 100MHz LVCMOS P -0.5% down-spread SSC 100MHz 85Ω LP-HCSL -0.5% down-spread SSC Disabled
Page 2 100MHz 85Ω LP-HCSL -0.3% down-spread SSC 100MHz LVCMOS P -0.3% down-spread SSC Disabled 100MHz 85Ω LP-HCSL -0.3% down-spread SSC Disabled 100MHz LVCMOS P -0.3% down-spread SSC 100MHz 85Ω LP-HCSL -0.3% down-spread SSC Disabled
Page 3 100MHz 85Ω LP-HCSL -0.25% down-spread SSC 100MHz LVCMOS P -0.25% down-spread SSC Disabled 100MHz 85Ω LP-HCSL -0.25% down-spread SSC Disabled 100MHz LVCMOS P -0.25% down-spread SSC 100MHz 85Ω LP-HCSL -0.25% down-spread SSC Disabled