SLUUDI1 December   2025 LMK3H2108

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2LMK3H2108 Configuration Summary
    1. 2.1  LMK3H2108A01
    2. 2.2  LMK3H2108A03
    3. 2.3  LMK3H2108A04
    4. 2.4  LMK3H2108A05
    5. 2.5  LMK3H2108A06
    6. 2.6  LMK3H2108A07
    7. 2.7  LMK3H2108A0D
    8. 2.8  LMK3H2108A0E
    9. 2.9  LMK3H2108A0F
    10. 2.10 LMK3H2108A11
    11. 2.11 LMK3H2108A14
    12. 2.12 LMK3H2108A15
    13. 2.13 LMK3H2108A16
    14. 2.14 LMK3H2108A17
    15. 2.15 LMK3H2108A18
  6. 3Revision History

2.9 LMK3H2108A0F

LMK3H2108A0F Configuration Guide

LMK3H2108A0F Register Map

Table 2-9 LMK3H2108A0F Configuration Summary
OTP Page OUT0 Config OUT1 Config OUT2 Config OUT3 Config OUT4 Config OUT5 Config OUT6 Config OUT7 Config
Page 0 100MHz 100Ω LP-HCSL 25MHz Differential LVCMOS 25MHz Differential LVCMOS 100MHz 100Ω LP-HCSL 100MHz 100Ω LP-HCSL Disabled 156.25MHz DC-LVDS 156.25MHz DC-LVDS
Page 1 100MHz 100Ω LP-HCSL 25MHz Differential LVCMOS 25MHz Differential LVCMOS 100MHz 100Ω LP-HCSL 100MHz 100Ω LP-HCSL Disabled 156.25MHz DC-LVDS 156.25MHz DC-LVDS
Page 2 100MHz 100Ω LP-HCSL 25MHz Differential LVCMOS 25MHz Differential LVCMOS 100MHz 100Ω LP-HCSL 100MHz 100Ω LP-HCSL Disabled 156.25MHz DC-LVDS 156.25MHz DC-LVDS
Page 3 100MHz 100Ω LP-HCSL 25MHz Differential LVCMOS 25MHz Differential LVCMOS 100MHz 100Ω LP-HCSL 100MHz 100Ω LP-HCSL Disabled 156.25MHz DC-LVDS 156.25MHz DC-LVDS