SLOA140B April   2009  – November 2018 TRF7960 , TRF7960A , TRF7961 , TRF7962A , TRF7963A

 

  1.   Using the SPI Interface With TRF7960
    1.     Trademarks
    2. 1 TRF7960 - SPI With SS* Mode Errata
      1. 1.1 SCLK Polarity Switch
      2. 1.2 IRQ Status Register Read
      3. 1.3 Direct Command Processing
      4. 1.4 Initialization of Derivative Registers
      5. 1.5 Transmitting One Byte Through the FIFO
      6. 1.6 Extra Dummy Bytes on RX
      7. 1.7 Timing Conditions for MOSI With Respect to S_CLK
  2.   Revision History

1.5 Transmitting One Byte Through the FIFO

When transmitting one byte to the TRF7960 using SPI with SS* mode, a special firmware fix is needed. This method involves splitting the writes into two operations as shown in the pseudo code below.

buf[0] = 0x8f;
buf[1] = 0x91;
buf[2] = 0x3d;
buf[3] = 0x00;
buf[4] = 0x10;
RAWwrite(&buf[0], 5);
buf[5] = 0x3F;
buf[6] = "one byte data to be transmitted";
buf[7] = 0x00;
RAWwrite(&buf[5], 3);

Each RAW Write function takes the SS low and high. Please refer to the TRF7960 firmware for definition of RAWwrite function. (file name parallel.c)