SLLA589 June 2022 TDP0604
This section describes the general pin configurations.
EN: When low, TDP0604 will be held in reset. The EN pin has a internal 250-kΩ pullup to VIO. For passive circuitry implementation, add an external 0.22-μF pulldown capacitor on the EN pin.
VIO: The TDP0604 supports 1.2-V, 1.8-V, and 3.3-V LVCMOS levels depending on the source I/O voltage requirement. The VIO pin is used to select which voltage level is used for the following 2-level control pins: LV_DDC_SDA, LV_DDC_SCL, SCL/CFG0, and SDA/CFG1.
| VIO Pin | LVCMOS Signaling Level |
|---|---|
| VIO < 1.5 V | 1.2 V |
| 1.5 V < VIO < 2.5 V | 1.8 V |
| VIO > 2.5 V | 3.3 V |
Mode (pin-strap or I2C mode): The MODE pin provides three modes of operation. There are two pin-strap modes and one I2C mode.
In pin-strap mode, if using the LV_DDC_SDA and LV_DDC_SCL for DDC snooping, the internal DDC buffer must be disabled. But if using the HV_DDC_SDA and HV_DDC_SCL for DDC snooping, the internal DDC buffer must be enabled.
In I2C mode, the DDC snoop feature is enabled by default but can be disabled by a register.
| Mode | Description |
|---|---|
| 0 | Pin-strap mode with internal DDC buffer enabled |
| R | Pin-strap mode with internal DDC buffer disabled |
| F | I2C mode |
SCL/CFG0: In pin-strap mode, this is the CFG0 pin. Tie this pin to '0' for normal HDMI mode. In I2C mode, this is the SCL pin.
SDA/CFG1: In pin-strap mode, this is the CFG1 pin. The CFG1 pin needs to set to '0' for normal lane ordering, but set to '1' if the input/output lane order is swapped. In I2C mode, this is the SDA pin.
LINEAR_EN pin: In pin-strap mode, the LINEAR_EN sets the TDP0604 into either linear or limited re-driver mode. For HDMI 1.4 and 2.0, set the LINEAR_EN to '0' for HDMI source application and 'F' for HDMI sink application.
HPDOUT_SEL: The HPDOUT_SEL selects whether the HPD_OUT pin is push-pull, or open-drain. Since open-drain is not supported in the pin-strap mode, this pin needs to be NC or pulled to ground.