SLAT161 June   2022 HD3SS3411 , TMUXHS4412

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2What is PCI Express (PCIe)?
    1. 2.1 PCIe Link
    2. 2.2 PCIe Clocking Architectures
      1. 2.2.1 Common Reference Clock
      2. 2.2.2 Data Reference Clock
      3. 2.2.3 Separate Reference Clock
    3. 2.3 PCIe Reference Clock Specification
  5. 3Reference Clock Measurement With TI Multiplexers
    1. 3.1 Test Setup and Procedure
      1. 3.1.1 Test Setup
      2. 3.1.2 Test Procedure
    2. 3.2 Test Report
      1. 3.2.1 Test Result With Clock Source
      2. 3.2.2 Test Result With HD3SS3411
      3. 3.2.3 Test Result With TMUXHS4412
      4. 3.2.4 Test Result With TMUXHS221
  6. 4Summary

2.1 PCIe Link

Before considering clocking architectures, examine the PCIe data link. It consists of one or more lanes that provide a transmit (Tx) and receive (Rx) differential pair. Figure 2-1 shows two devices that need to transfer data. One of the key advantages of PCIe is its bandwidth scalability enabling up to 32 lanes to be configured on a single link. Table 2-1 is the data rate vs different PCIe standard.

GUID-20220628-SS0I-P0WT-RSGD-6CS6HR7L5M9H-low.png Figure 2-1 PCIe Link
Table 2-1 PCIe Standard Versus Bit Rate
PCIe Standard Raw Bit Rate
PCIe 1.1 2.5 GBit/s
PCIe 2.1 5.0 GBit/s
PCIe 3.1 8.0 GBit/s
PCIe 4.0 16.0 GBit/s
PCIe 5.0 32.0 GBit/s