SLAAED8A October 2024 – July 2026 TAC5111 , TAC5112 , TAC5211 , TAC5212 , TAC5412-Q1 , TAD5112 , TAD5212
The powerup delay timer is the time by which the user can delay the beginning of the first chirp cycle, from when the playback path is powered up by setting the DAC_PDz bit (B0_P0_R120[6]). For instance, a powerup delay of 500ms would mean that the first chirp cycle starts 500ms after powering up the playback path. The minimum powerup delay that can be programmed is 127ms.
The powerup delay follows the equation:
To program the powerup delay into the registers listed in Table 3-5:
| Page | Register | Default Powerup Delay time at 48kHz sampling rate | Value |
| 0x17 | 0x74 | Powerup Delay = 207 ms (0x00002580) | APWRUP [31:24] |
| 0x17 | 0x75 | APWRUP [23:16] | |
| 0x17 | 0x76 | APWRUP [15:8] | |
| 0x17 | 0x77 | APWRUP [7:0] |