4 Analog Input to PWM Output

The designer can use the 555 timer in monostable operation to generate a PWM signal by applying a trigger input with the desired frequency on the TRIG pin and an analog-input modulation voltage on the CONT pin. Figure 4-1 shows a configuration in which a negative transition on the TRIG pin goes below the trigger threshold of ⅓ × VDD, causing the flip-flop output (Q) to transition low, which drives OUT high and turns off the discharge path. With the discharge path turned off, C is charged through R_A, and continues until the voltage of the capacitor on the THRESH pin exceeds that of the analog input applied to the CONT pin. When the input waveform on the TRIG pin has returned to a high level, the flip-flop is reset, Q transitions high, the output is driven low, and the capacitor discharges through the discharge path. The negative pulse on TRIG must be shorter than the shortest expected output pulse determined by RC and the voltage on the CONT pin, otherwise the device will retrigger and the output voltage will remain high.

The RC time constant of R_A × C should be selected to equal approximately ¼ of the period of the pulse train input to the TRIG pin. 4 × R_A × C is the estimated time to transition from 0 V to VDD, therefore selecting components with this relationship will allow for a full charge within one pulse train period input to the TRIG pin.

This combination of behaviors achieves a PWM function. The main limitation from this circuit is that a traditional PWM scheme relies on a linear function to modulate the analog input signal. In this case, the PWM transfer function is based on the exponential voltage response of the capacitor charging — this aligns with a linear function for lower voltages applied to the CONT pin, but begins to deviates from the linear function for higher voltages.

Figure 4-2 shows the resulting waveforms for PWM applied to a 1-kHz input sine wave with a trigger frequency of 100-kHz.

Smart DACs are superior for creating PWM signals. A PWM output is generated by using the DAC53701 in CWG mode and applying a modulation input voltage, VFB, to the feedback pin of the DAC as shown in Figure 4-3. The equations for frequency and duty cycle will be the same as Equation 11 and Equation 12. The duty cycle will have a linear relationship with the modulation input.

Figure 4-4 shows a 10-kHz triangle wave produced by the DAC53701 and a 1-kHz, 700 mV peak input sine wave centered at 3 V applied to the modulation input. To achieve a faster PWM signal, the slew rate can be lowered, the code step can be increased, or the number of codes between margin-high and margin-low can be minimized. The modulation input must also be scaled accordingly to not exceed the margin-high and margin-low voltages.