SFFSB91 May 2026 TXE8148
4.1 TSSOP Package
This section provides a failure mode analysis (FMA) for the pins of the TXE8148. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to VCC (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Table 4-1 shows the TXE8148 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TXE8148 datasheet.
Figure 4-1 Pin DiagramTable 4-2 Pin FMA for Device Pins Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| INT | 1 | The interrupt function is stuck low, and the functionality of the pin is lost. | B |
| RESET/FAIL-SAFE | 2 | The device is held in reset and all functionality of the pin is lost. All the Px.y pins remain Hi-Z. | B |
| GND | 3 | There is no effect on the device. GND is the intended connection for this pin. | D |
| VCC | 4 | The device is held in reset and all functionality of the pin is lost. All the Px.y pins become Hi-Z. | B |
| P0.0 –
P0.7 P1.0 – P1.7 P2.0 – P2.7 P3.0 – P3.7 P4.0 – P4.7 P5.0 – P5.7 | 5 – 52 | If the pin is configured to be an output high, damage to the P-Channel FET potentially occurs due to high current draw. | A |
| If the pin is configured as an input or output low, functionality of the pin is lost. | B | ||
| CS | 53 | Chip select is always in an active state, and SPI communication is not possible. | B |
| SCLK | 54 | The communication clock is stuck in a logic-low state, disabling the data shift register from the SDI pin and not allowing SDO data to be available to the controller. | B |
| SDI | 55 | The SDI pin is stuck in a logic-low state, which does not allow any data from the controller to be sent through the SPI to the device. | B |
| SDO | 56 | The push-pull SDO pin is stuck in a logic-low state. Damage to the P-Channel FET potentially occurs due to high current draw when driving logic-high during communication. | A |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| INT | 1 | The INT pin can no longer assert low, and the controller cannot be notified of interrupts. | B |
| RESET/FAIL-SAFE | 2 | A floating RESET pin potentially makes the device unresponsive or affects the programmed pin functions if the pin floats to logic-low. | B |
| GND | 3 | The device is not biased to GND. There is damage to the device if GND floats high or low excessively. | A |
| VCC | 4 | The functionality of the pin is lost. | B |
| P0.0 –
P0.7 P1.0 – P1.7 P2.0 – P2.7 P3.0 – P3.7 P4.0 – P4.7 P5.0 – P5.7 | 5 – 52 | If the pin is configured to be an input, higher in-rush supply current potentially triggers the INT pin due to a floating input. | B |
| If the pin is configured as an output, there is no damage to device. | D | ||
| CS | 53 | A floating CS pin potentially makes SPI communication indeterminate, and the functionality of the pin is lost. | B |
| SCLK | 54 | A floating SCLK pin potentially makes SPI communicate indeterminate, disabling the data shift register from the SDI pin and not allowing SDO data to be available to the controller. | B |
| SDI | 55 | A floating SDI pin potentially causes incorrect data to be latched, and the functionality of the pin is lost. | B |
| SDO | 56 | The push-pull SDO pin is stuck in a logic-low state. Damage to the P-Channel FET potentially occurs due to high current draw when driving logic-high during communication. | A |
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| INT | 1 | RESET/FAIL-SAFE | The device goes into RESET when an interrupt is triggered and functionality is lost. | B |
| RESET/FAIL-SAFE | 2 | GND | If the RESET pin is shorted to ground, the device is in a reset state and the functionality of the pin is lost . | A |
| GND | 3 | VCC | The device is not powered and all functionality is lost. | B |
| VCC | 4 | P1.0 | If the P1.0 pin is configured as an output with a logic high level, no issues with the pin are expected. | D |
| If the P1.0 pin is configured as an output with a logic low level, then contention between the pins occurs. If the IOH specification is exceeded, then damage to the device potentially occurs. | A | |||
| If the P1.0 pin is configured as an input, then damage to the device does not occur. | D | |||
| P1.0 | 5 | P1.1 | If pins P1.0 and P1.1 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P1.0 and P1.1 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P1.0 and P1.1 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P1.0 and P1.1 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P1.1 | 6 | P1.2 | If pins P1.1 and P1.2 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P1.1 and P1.2 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P1.1 and P1.2 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P1.1 and P1.2 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P1.2 | 7 | P1.3 | If pins P1.2 and P1.3 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P1.2 and P1.3 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P1.2 and P1.3 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P1.2 and P1.3 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P1.3 | 8 | P1.4 | If pins P1.3 and P1.4 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P1.3 and P1.4 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P1.3 and P1.4 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P1.3 and P1.4 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P1.4 | 9 | P1.5 | If pins P1.4 and P1.5 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P1.4 and P1.5 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P1.4 and P1.5 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P1.4 and P1.5 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P1.5 | 10 | P1.6 | If pins P1.5 and P1.6 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P1.5 and P1.6 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P1.5 and P1.6 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P1.5 and P1.6 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P1.6 | 11 | P1.7 | If pins P1.6 and P1.7 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P1.6 and P1.7 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P1.6 and P1.7 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P1.6 and P1.7 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P1.7 | 12 | P2.0 | If pins P1.7 and P2.0 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P1.7 and P2.0 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P1.7 and P2.0 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P1.7 and P2.0 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P2.0 | 13 | P2.1 | If pins P2.0 and P2.1 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P2.0 and P2.1 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P2.0 and P2.1 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P2.0 and P2.1 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P2.1 | 14 | P2.2 | If pins P2.1 and P2.2 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P2.1 and P2.2 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P2.1 and P2.2 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P2.1 and P2.2 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P2.2 | 15 | P2.3 | If pins P2.2 and P2.3 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P2.2 and P2.3 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P2.2 and P2.3 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P2.2 and P2.3 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P2.3 | 16 | P2.4 | If pins P2.3 and P2.4 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P2.3 and P2.4 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P2.3 and P2.4 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P2.3 and P2.4 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P2.4 | 17 | P2.5 | If pins P2.4 and P2.5 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P2.4 and P2.5 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P2.4 and P2.5 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P2.4 and P2.5 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P2.5 | 18 | P2.6 | If pins P2.5 and P2.6 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P2.5 and P2.6 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P2.5 and P2.6 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P2.5 and P2.6 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P2.6 | 19 | P2.7 | If pins P2.6 and P2.7 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P2.6 and P2.7 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P2.6 and P2.7 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P2.6 and P2.7 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P2.7 | 20 | P3.0 | If pins P2.7 and P3.0 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P2.7 and P3.0 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P2.7 and P3.0 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P2.7 and P3.0 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P3.0 | 21 | P3.1 | If pins P3.0 and P3.1 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P3.0 and P3.1 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P3.0 and P3.1 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P3.0 and P3.1 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P3.1 | 22 | P3.2 | If pins P3.1 and P3.2 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P3.1 and P3.2 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P3.1 and P3.2 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P3.1 and P3.2 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P3.2 | 23 | P3.3 | If pins P3.2 and P3.3 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P3.2 and P3.3 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P3.2 and P3.3 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P3.2 and P3.3 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P3.3 | 24 | P3.4 | If pins P3.3 and P3.4 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P3.3 and P3.4 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P3.3 and P3.4 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P3.3 and P3.4 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P3.4 | 25 | P3.5 | If pins P3.4 and P3.5 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P3.4 and P3.5 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P3.4 and P3.5 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P3.4 and P3.5 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P3.5 | 26 | P3.6 | If pins P3.5 and P3.6 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P3.5 and P3.6 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P3.5 and P3.6 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P3.5 and P3.6 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P3.6 | 27 | P3.7 | If pins P3.6 and P3.7 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P3.6 and P3.7 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P3.6 and P3.7 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P3.6 and P3.7 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P5.0 | 29 | P5.1 | If pins P5.0 and P5.1 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P5.0 and P5.1 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P5.0 and P5.1 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P5.0 and P5.1 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P5.1 | 30 | P5.2 | If pins P5.1 and P5.2 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P5.1 and P5.2 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P5.1 and P5.2 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P5.1 and P5.2 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P5.2 | 31 | P5.3 | If pins P5.2 and P5.3 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P5.2 and P5.3 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P5.2 and P5.3 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P5.2 and P5.3 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P5.3 | 32 | P5.4 | If pins P5.3 and P5.4 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P5.3 and P5.4 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P5.3 and P5.4 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P5.3 and P5.4 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P5.4 | 33 | P5.5 | If pins P5.4 and P5.5 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P5.4 and P5.5 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P5.4 and P5.5 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P5.4 and P5.5 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P5.5 | 34 | P5.6 | If pins P5.5 and P5.6 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P5.5 and P5.6 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P5.5 and P5.6 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P5.5 and P5.6 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P5.6 | 35 | P5.7 | If pins P5.6 and P5.7 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P5.6 and P5.7 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P5.6 and P5.7 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P5.6 and P5.7 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P5.7 | 36 | P4.0 | If pins P5.7 and P4.0 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P5.7 and P4.0 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P5.7 and P4.0 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P5.7 and P4.0 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P4.0 | 37 | P4.1 | If pins P4.0 and P4.1 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P4.0 and P4.1 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P4.0 and P4.1 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P4.0 and P4.1 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P4.1 | 38 | P4.2 | If pins P4.1 and P4.2 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P4.1 and P4.2 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P4.1 and P4.2 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P4.1 and P4.2 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P4.2 | 39 | P4.3 | If pins P4.2 and P4.3 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P4.2 and P4.3 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P4.2 and P4.3 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P4.2 and P4.3 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P4.3 | 40 | P4.4 | If pins P4.3 and P4.4 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P4.3 and P4.4 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P4.3 and P4.4 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P4.3 and P4.4 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P4.4 | 41 | P4.5 | If pins P4.4 and P4.5 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P4.4 and P4.5 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P4.4 and P4.5 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P4.4 and P4.5 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P4.5 | 42 | P4.6 | If pins P4.5 and P4.6 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P4.5 and P4.6 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P4.5 and P4.6 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P4.5 and P4.6 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P4.6 | 43 | P4.7 | If pins P4.6 and P4.7 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P4.6 and P4.7 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P4.6 and P4.7 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P4.6 and P4.7 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P4.7 | 44 | P0.0 | If pins P4.7 and P0.0 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P4.7 and P0.0 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P4.7 and P0.0 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P4.7 and P0.0 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P0.0 | 45 | P0.1 | If pins P0.0 and P0.1 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P0.0 and P0.1 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P0.0 and P0.1 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P0.0 and P0.1 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P0.1 | 46 | P0.2 | If pins P0.1 and P0.2 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P0.1 and P0.2 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P0.1 and P0.2 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P0.1 and P0.2 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P0.2 | 47 | P0.3 | If pins P0.2 and P0.3 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P0.2 and P0.3 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P0.2 and P0.3 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P0.2 and P0.3 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P0.3 | 48 | P0.4 | If pins P0.3 and P0.4 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P0.3 and P0.4 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P0.3 and P0.4 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P0.3 and P0.4 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P0.4 | 49 | P0.5 | If pins P0.4 and P0.5 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P0.4 and P0.5 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P0.4 and P0.5 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P0.4 and P0.5 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P0.5 | 50 | P0.6 | If pins P0.5 and P0.6 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P0.5 and P0.6 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P0.5 and P0.6 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P0.5 and P0.6 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P0.6 | 51 | P0.7 | If pins P0.6 and P0.7 are configured as outputs with opposite logic levels, then contention between the pins occur. If the IOH specification is exceeded, then damage to the device potentially occurs. | A |
| If pins P0.6 and P0.7 are configured as outputs with the same logic level, then damage to the device does not occur. | D | |||
| If pins P0.6 and P0.7 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| If pins P0.6 and P0.7 are configured as inputs, then no damage to the device is expected, but this configuration potentially leads to false interrupts. | C | |||
| P0.7 | 52 | CS | If pin P0.7 is an input, false interrupts potentially occur when the CS pin toggles. | C |
| If pin P0.7 is as output, CS is potentially unusable and functionality is lost. | B | |||
| CS | 53 | SCLK | The CS pin toggles with the SCLK pin, SPI communication is not usable, and functionality is lost. | B |
| SCLK | 54 | SDI | SPI communication to the device is incorrect and functionality is lost. | B |
| SDI | 55 | SDO | SPI communication to the device is incorrect and functionality is lost. | B |
Table 4-5 Pin FMA for Device Pins Short-Circuited to VCC
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| INT | 1 | If the INT pin is asserted low, damage to the N-Channel FET potentially occurs due to high current sink. |
A |
| RESET / FAIL-SAFE | 2 | If the RESET pin is tied to a pullup voltage, then higher leakage currents potentially occur. |
C |
| If the RESET pin is tied to a pullup voltage, and an external circuit attempts to drive the RESET, the device is not able to be reset through this hardware pin. | B | ||
| GND | 3 | The device is not powered and all functionality is lost. | B |
| VCC | 4 | There is no effect on the device. This is the intended use of this pin. | D |
| P0.0 –
P0.7 P1.0 – P1.7 P2.0 – P2.7 P3.0 – P3.7 P4.0 – P4.7 P5.0 – P5.7 | 5 – 52 | If the pin is configured as an input or output high, the functionality of the pin is lost. | B |
| If the pin is configured to be an output low, damage to the N-Channel FET potentially occurs due to high current sink. | A | ||
| CS | 53 | The chip select pin is stuck in the logic-high state, SPI communication is not possible. | B |
| SCLK | 54 | The communication clock is stuck in a logic-low state, disabling the data shift register from the SDI pin and not allowing SDO data to be available to the controller. | B |
| SDI | 55 | The SDI pin is stuck in a logic-low state, which does not allow any data from the controller to be sent through the SPI to the device. | B |
| SDO | 56 | The push-pull SDO pin is stuck in a logic-high state. Damage to the N-Channel FET potentially occurs due to high current sink when driving logic-high during communication. | A |