SFFSAR6 August   2025 TPS3842

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the TPS3842. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality.
BNo device damage, but loss of functionality.
CNo device damage, but performance degradation.
DNo device damage, no impact to functionality or performance.

Figure 4-1 shows the TPS3842 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section of the TPS3842 data sheet.

Figure 4-1 Pin Diagram DRL Package 6-Pin SOT5X3

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • At VDD (MIN) ≤ VDD ≤ VDD (MAX)
  • CTS = Open, CTR = Open
  • Output reset pullup resistor (RPULLUP) = 10kΩ, output reset pullup voltage (VPULLUP = 3.3V)
  • Sense is monitoring VDD
  • Typical values are at TA = 25°C, VDD = 3.3V, CVDD= 0.1µF, and VITN = 0.7V; unless stated otherwise.
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description Of Potential Failure EffectsFailure Effect Class
VDD1VDD short to GND; device has no power for normal operation.B
SENSE2RESET asserts.B
RESET3Forces RESET low.B
CTS4RESET is unable to assert.B
GND5No damage to the device. No impact to the functionality of the device.D
CTR6RESET asserts normally but does not deassert.B
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
VDD1Device is not powered.B
SENSE2No damage to the device. Reset asserts.B
RESET3Reset functionality is lost since reset is not pulled up to VDD.B
CTS4Normal operation.D
GND5Device is not powered.B
CTR6Normal operation.D
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted To Description of Potential Failure Effects Failure Effect Class
VDD 1 SENSE Normal functionality if SENSE is monitoring VDD rail. RESET asserts if VDD < Vitn. D
2
SENSE 2 RESET RESET follows VSENSE; giving instances of wrong outputs. C
3
CTS 4 GND RESET is unable to assert. B
5
GND 5 CTR RESET asserts normally but does not deassert. B
6
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
VDD1No damage to the device. No impact to the functionality of the device.D
SENSE2RESET asserts if VDD < Vitn; otherwise, normal functionality.D
RESET3Forces RESET high.B
CTS4No damage to the device. No impact to the functionality of the device.D
GND5GND short to VDD; device has no power for normal operation.D
CTR6RESET asserts.B