SFFSAO3 September   2025 UCC33411-Q1 , UCC33421-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SSOP-16 Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SSOP-16 Package
  7. 5Revision History

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the UCC33011(Q1), UCC33021(Q1), UCC33411(Q1), and UCC33421(Q1) (SSOP-16 package). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality.
BNo device damage, but loss of functionality.
CNo device damage, but performance degradation.
DNo device damage, no impact to functionality or performance.

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • The device is configured according to the Typical Application in the Application and Implementation section of the data sheet.
  • The VINP pin is considered the supply pin for primary-side pins.
  • The GNDP pin is considered the ground for primary-side pins.
  • The VCC pin is considered the supply pin for secondary-side pins.
  • The GNDS pin is considered the ground for secondary-side pins.
  • The primary-side pins only short to the primary-side pins. The secondary side-pins only short to the secondary-side pins.