SFFSA81 March 2025 OPA810-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the OPA810-Q1 (SOT-23 | DBV package). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to V+ (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality.
B	No device damage, but loss of functionality.
C	No device damage, but performance degradation.
D	No device damage, no impact to functionality or performance.

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

A total supply voltage of 10V, with the V+ connected to 5V and the V- connected to -5V.
The input and output pins are biased to a GND reference point.
The device is configured with the feedback network in a gain greater than or equal to 1V/V.