SFFSA38 November 2024 LM644A2-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the LM644xx-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1, Figure 4-2, and Figure 4-3 show the LM644xx-Q1 pin diagrams. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM644xx-Q1 data sheet.
Figure 4-1 Dual Pin Diagram
Figure 4-2 Single Primary Pin Diagram
Figure 4-3 Single Secondary Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Application circuit, per the LM644A2-Q1 data sheet is used.
| Pin Name | Pin No | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VIN2 | 1 | VOUT = 0V. | B |
| CB2 | 2 | VOUT = 0V. | B |
| SW2 | 3 | Potential damage to high-side FET. | A |
| PGND3 | 4 | Normal operation. | D |
| SW1 | 5 | Potential damage to high-side FET. | A |
| CB1 | 6 | VOUT = 0V. | B |
| VIN1 | 7 | VOUT = 0V. | B |
| SERIES_CAP1 | 8 | Series capacitor is shorted internally. Device bypassing capacitance increases as two-series capacitors become single capacitor. | D |
| PGND1 | 9 | Normal operation. | D |
| SYNC | 10 | Normal operation for PFM mode. | C |
| PG1 | 11 | Loss of power good flag. | B |
| MODE | 11 | Normal operation for PFM mode. | C |
| EN1 | 12 | Device is disabled. | C |
| BIAS/VOSNS1 | 13 | VOUT1 = 0V short circuit. | B |
| FB1 | 14 | If configured as 3.3V fixed, normal operation. If configured for other Vout, then Vout1 is out of specification and outputs 3.3V. | B |
| VCC | 15 | Device is disabled. | B |
| AGND | 16 | Normal operation. | D |
| RT | 17 | VOUT = 0V. No switching. | B |
| FB2 | 18 | If configured as 3.3V fixed, normal operation. If configured for other Vout, then Vout2 is out of specification and outputs 3.3V. | B |
| SS | 18 | VOUT = 0V. | B |
| VOSNS2 | 19 | VOUT2 = 0V, if FB2 = VCC or GND. | B/C |
| COMP | 19 | VOUT = 0V. | B |
| EN2 | 20 | Second channel is disabled. | B |
| CONFIG | 21 | Device is configured as dual output voltage. | B |
| PG2 | 22 | Loss of power good flag. | B |
| SYNCOUT | 22 | If primary, secondary, and tertiary devices do not switch. If secondary or tertiary device does not switch. If tertiary, no effect. | B |
| PGND2 | 23 | Normal operation. | D |
| SERIES_CAP2 | 24 | Series capacitor is shorted internally. Device bypassing capacitance increases as two-series capacitors become single capacitor. | D |
| PGND | 25 | Normal operation. | D |
| Pin Name | Pin No | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VIN2 | 1 | VOUT2 = 0V. | B |
| CB2 | 2 | VOUT2 collapses under load as FET gate voltage is not enough to fully enhance. Damage can occur if current is pulled from switch. | A |
| SW2 | 3 | VOUT2 = 0V. | B |
| PGND3 | 4 | Normal operation. | D |
| SW1 | 5 | VOUT1 = 0V. | B |
| CB1 | 6 | VOUT1 collapses under load as FET gate voltage is not enough to fully enhance. Damage can occur if current is pulled from switch. | A |
| VIN1 | 7 | VOUT1 = 0V. | B |
| SERIES_CAP1 | 8 | Normal operation. | D |
| PGND1 | 9 | Normal operation. | D |
| SYNC | 10 | Device can toggle between PFM and PWM modes. | C |
| PG1 | 11 | Loss of power good flag. | B |
| MODE | 11 | Device can toggle between PFM and PWM modes. | C |
| EN1 | 12 | Loss of disable function. | C |
| BIAS/VOSNS1 | 13 | If in fixed output configuration, Vout is greater than set point. If in adjustable Vout configuration, slight increase in input current. | B |
| FB1 | 14 | Part configuration is randomly selected between fixed 5V or adjustable. | B/C |
| VCC | 15 | Part can turn on and off as VCC UVLO is triggered. | B |
| AGND | 16 | Normal operation. | D |
| RT | 17 | VOUT = 0V. No switching. | B |
| FB2 | 18 | Part configuration is randomly selected between fixed 5V or adjustable. | B/C |
| SS | 18 | Fast soft start. | D |
| VOSNS2 | 19 | If in fixed output configuration, Vout is greater than set point. | B |
| COMP | 19 | Device can have oscillations on VOUT. | B |
| EN2 | 20 | Loss of disable function. | C |
| CONFIG | 21 | VOUT = 0V. No switching. | B |
| PG2 | 22 | Loss of power good flag. | B |
| SYNCOUT | 22 | If primary, secondary, and tertiary devices do not switch. If secondary or tertiary device does not switch. If tertiary, no effect. | B |
| PGND2 | 23 | Normal operation. | D |
| SERIES_CAP2 | 24 | Normal operation. | D |
| PGND | 25 | Normal operation. | D |
| Pin Name | Pin No | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| VIN2 | 1 | CB2 | Boot driver is damaged. | A |
| CB2 | 2 | SW2 | VOUT2 = 0. | B |
| SW2 | 3 | PGND3 | Potential damage to high-side FET. | A |
| PGND3 | 4 | SW1 | Potential damage to high-side FET. | A |
| SW1 | 5 | CB1 | VOUT1 = 0. | B |
| CB1 | 6 | VIN1 | Boot driver is damaged. | A |
| VIN1 | 7 | SERIES_CAP1 | Series capacitor is shorted internally. Device bypassing capacitance increases as two-series capacitors become single capacitor. | D |
| SERIES_CAP1 | 8 | PGND1 | Series capacitor is shorted internally. Device bypassing capacitance increases as two-series capacitors become single capacitor. | D |
| PGND1 | 9 | SYNC | Normal operation for AUTO mode. | C |
| SYNC | 10 | PG1 | For PG < 5.5V, device starts in PFM and
transition to PWM after start up. For PG > 5.5V, damage can occur. For mode, part can enter PFWM of PWM mode based on SYNC logic. |
A |
| PG1 | 11 | MODE | For EN < 20V, device damage can occur if
PG FET current limit is exceeded. For EN > 20V, PGOOD FET can be damaged. |
A |
| MODE | 11 | EN1 | For EN < 20V, normal operation. For EN > 20V, PGOOD FET can be damaged. |
A |
| EN1 | 12 | BIAS/VOSNS1 | For EN < 5V, output voltage out of
range. For EN > 5V, device damage can occur if current is not limited. |
A |
| BIAS/VOSNS1 | 13 | FB1 | If configured as 3.3V fixed, normal
operation. If configured for other Vout, then Vout1 is out of specification and outputs 3.3V. |
B |
| FB1 | 14 | VCC | If configured as 5V fixed, normal
operation. If configured for other Vout, then Vout1 is out of specification and output 5V. |
B |
| VCC | 15 | AGND | Vout1 = Vout2 = 0V. | B |
| AGND | 16 | RT | VOUT = 0V. No switching. | B |
| RT | 17 | FB2 | Switching frequency and output voltage is incorrect. | B |
| FB2 | 18 | SS | If FB2 is grounded, Vout2 is greater than
set point. If FB2 is VCC then VCC is pulled to 5V, damage is unlikely to occur. If FB2 is resistor divider, the Vout is 3.3Vout and there is a load from the FB resistance to ground. |
B |
| SS | 18 | VOSNS2 | Fast soft start. | C |
| VOSNS2 | 19 | COMP | VOUT2is greater than set point. | B |
| COMP | 19 | EN2 | EN > 5.5V, damage of comparator if not current limited. | A |
| EN2 | 20 | CONFIG | EN2 < 5.5V, device is configured as dual
output voltage. EN2 > 5.5, damage if not current limited. |
A |
| CONFIG | 21 | PG2 | Device is configured as dual output voltage. | B |
| PG2 | 22 | SYNCOUT | Loss of power good flag. | B |
| SYNCOUT | 22 | PGND2 | If primary, secondary, and tertiary devices
do not switch. If secondary or tertiary device does not switch. If tertiary, no effect. |
B |
| PGND2 | 23 | SERIES_CAP2 | Normal operation. | D |
| SERIES_CAP2 | 24 | PGND | Series capacitor is shorted internally. Device bypassing capacitance increases as two-series capacitors become single capacitor. | D |
| PGND | 25 | VIN2 | Series capacitor is shorted internally. Device bypassing capacitance increases as two-series capacitors become single capacitor. | D |
| Pin Name | Pin No | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VIN2 | 1 | Normal operation. | D |
| CB2 | 2 | Boot driver is damaged. | A |
| SW2 | 3 | Potential damage to low-side FET. | A |
| PGND3 | 4 | VOUT = 0V. | B |
| SW1 | 5 | Potential damage to low-side FET. | A |
| CB1 | 6 | Boot driver is damaged. | A |
| VIN1 | 7 | Normal operation. | D |
| SERIES_CAP1 | 8 | Series capacitor is shorted internally. Device bypassing capacitance increases as two-series capacitors become single capacitor. | D |
| PGND1 | 9 | VOUT = 0V. | B |
| SYNC | 10 | Potential damage for VIN > 5.5V. | A |
| PG1 | 11 | Loss of power good flag. Potential damage if not current limited. | A |
| MODE | 11 | Normal operation for PWM mode. Potential damage for VIN > 5.5V. | A |
| EN1 | 12 | Device is enabled. | C |
| BIAS/VOSNS1 | 13 | Potential damage from permanent short across converter. | A |
| FB1 | 14 | Potential damage for VIN > 5.5V. | A |
| VCC | 15 | Potential damage for VIN > 5.5V. | A |
| AGND | 16 | VOUT = 0V. | B |
| RT | 17 | Potential damage for VIN > 5.5V. | A |
| FB2 | 18 | Potential damage for VIN > 5.5V. | A |
| SS | 18 | Potential damage for VIN > 5.5V. | A |
| VOSNS2 | 19 | Potential damage for VIN > 5.5V. | A |
| COMP | 19 | Potential damage for VIN > 5.5V. | A |
| EN2 | 20 | Second channel is enabled. | C |
| CONFIG | 21 | Potential damage for VIN > 5.5V. | A |
| PG2 | 22 | Potential damage for VIN > 20V, or lower, if not current limited. | A |
| SYNCOUT | 22 | Potential damage for VIN > 5.5V, or lower, if not current limited. | A |
| PGND2 | 23 | VOUT = 0V. | B |
| SERIES_CAP2 | 24 | Series capacitor is shorted internally. Device bypassing capacitance increases as two-series capacitors become single capacitor. | D |
| PGND | 25 | VOUT = 0V. | B |