SFFS855A December   2024  – June 2026 LMR60430-Q1 , LMR60440 , LMR60440-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 RAK Package
    2. 2.2 RBM Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 RAK Package
    2. 4.2 RBM Package
  7. 5Revision History

4.1 RAK Package

Figure 4-1 shows the LMR60430, LMR60430-Q1, LMR60440, and LMR60440-Q1 pin diagram for the RAK package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the LMR60430, LMR60430-Q1, LMR60440, and LMR60440-Q1 datasheet.

Figure 4-1 Pin Diagram (RAK Package)
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
VIN 1 VOUT = 0V. B
PGND 2 VOUT is normal. D
SW 3 Damage to high-side FET. A
BOOT 4 VOUT = 0V. High-side FET does not turn on. B
PG 5 When not in use, this pin can be left grounded (PG is not a valid signal and VOUT is normal). D
FB 6 When in adjustable output mode, VOUT approaches VIN. When in fixed output mode, VOUT = 0V. B
MODE/SYNC 7 Device switches in AUTO mode. VOUT is normal. D
RT 8 Device stops switching until short to GND is removed. B
EN 9 VOUT = 0V. Enable is below the VEN-TH and functionality is halted. D
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
VIN 1 VOUT = 0V. B
PGND 2 VOUT can be abnormal. C
SW 3 VOUT = 0V. B
BOOT 4 VOUT = 0V. High-side FET does not turn on. B
PG 5 When not in use, this pin can be left open (PGOOD is not a valid signal and VOUT is normal). D
FB 6 VOUT approaches VIN. C
MODE/SYNC 7 Mode of operation can toggle between AUTO and FPWM. C
RT 8 Internal clock does not operate properly and the part does not switch. B
EN 9 Pin cannot be left floating. Device potentially does not enable. B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effects Failure Effect Class
VIN 1 PGND VOUT = 0V. B
PGND 2 SW Damage to high-side FET. A
SW 3 BOOT VOUT = 0V, high-side FET does not turn on and there is not CBOOT. B
BOOT 4 PG PG damage occurs if BOOT voltage is greater than PG absolute maximum voltage. B
PG 5 FB In fixed output mode, VOUT = 0V. In adjustable mode, if a short happens before soft state is complete, output voltage approaches input voltage supply. B
FB 6 PGND In fixed output mode, VOUT = 0V. In adjustable output mode, output voltage approaches the input voltage supply. B
MODE/SYNC 7 RT Device operates in FPWM. D
RT 8 EN Internal clock does not switch at the correct frequency. C
EN 9 VIN Device is enabled once the voltage between VIN and PGND is greater than VINUVLO(R). D
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
VIN 1 VOUT is normal. D
PGND 2 VOUT = 0V. B
SW 3 Damage to low-side FET. A
BOOT 4 Damage occurs to BOOT ESD. A
PG 5 If supply voltage is greater than 20V, damage occurs to PGOOD pin. A
FB 6 If supply voltage is greater than 16V, damage occurs. A
MODE/SYNC 7 Device operates in FPWM. D
RT 8 Internal clock does not switch at the correct frequency. C
EN 9 VOUT is normal. D