SFFS169A April   2022  – May 2022 TPS3704 , TPS3704-Q1

 

  1. 1Introduction
    1.     Trademarks
  2. 2 TPS3704x-Q1 Hardware Component Functional Safety Capability
  3. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
    2. 3.2 TI Functional Safety Development Process
  4. 4 TPS3704x-Q1 Component Overview
    1. 4.1 Targeted Applications
    2. 4.2 Hardware Component Functional Safety Concept
    3. 4.3 Functional Safety Constraints and Assumptions
  5. 5Description of Hardware Component Parts
  6. 6 TPS3704x-Q1 Management of Random Faults
    1. 6.1 Fault Reporting
    2. 6.2 Functional Safety Mechanism Categories
    3. 6.3 Description of Functional Safety Mechanisms
      1.      A Summary of Recommended Functional Safety Mechanism Usage
        1.       B Distributed Developments
          1.        B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
          2.        B.2 Activities Performed by Texas Instruments
          3.        B.3 Information Provided
            1.         C Revision History

6.3 Description of Functional Safety Mechanisms

This section provides a brief summary of the functional safety mechanisms available on this component.

SM01 - OTP Write Protection

The OTP Write Protection ensures that the OTP cells are only written to when necessary. 2 Key Security- Fast slew rate input pulses, Secure sequence along with Clock, Fast Clocking required to enable OTP write. OTP Lock bits set after programming with Checksum bit for data verification. This method prevents rewrite of OTP in production. Checksum Bit verifies data integrity.

SM02 - SENSEx UV

For each Sense channel n(1..4), the TPS3704x-Q1 shall assert RESET_UV when the voltage on the SENSEn pin is less than the programmed OTP_UV_VALn threshold for a time-interval longer than the sense propagation delay tPD.

SM03 - SENSEx OV

For each Sense channel n(1..4), the TPS3704x-Q1 shall assert RESET_OV when the voltage on the SENSEn pin is greater than the programmed OTP_OV_VALn threshold for a time-interval longer than the sense propagation delay tPD.

SM04 - Configuration Checksum

OTP Checksum bit shall be checked at system startup before latch load to confirm OTP integrity. RESET will not be released at startup if there is a checksum mismatch

SME03 - RESET verifcation at startup

The TPS3704x-Q1 Shall assert all available RESET outputs during startup and release once Device has reached Safe active state. Host to Monitor RESET outputs at startup and confirm assertion, followed by de-assertion on expected timeline. This method can be used to detect issues with RESET pins, unexpected delays in RESET reponse, Issues with Latch logic, etc.