SFFS058A March   2021  – December 2021 DRV8245-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SPI "S" and "P" variant in HTSSOP package
    2. 4.2 SPI "S" variant in VQFN-HR package
    3. 4.3 HW variant in HTSSOP package
    4. 4.4 HW variant in VQFN-HR package
  6. 5Revision History

4.1 SPI "S" and "P" variant in HTSSOP package

Figure 4-2 shows the pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the DRV8245-Q1 data sheet.

Figure 4-2 SPI "S" and "P" variants
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin Description of Potential Failure Effect(s) Failure Effect Class
No. Name
1 SCLK SPI communication is lost. B
2 nSCS SPI communication is lost. B
3 PH/IN2 Normal function as register bit is used for direction control. D
4 EN/IN1 Load will be in re-circulation (braking). No risk of spin direction reversal. B
5 DRVOFF Pin based shutoff function is lost. B
6, 7, 8, 21, 22, 23 VM Device is powered off with driver Hi-Z. B
9, 10, 11 OUT1 If OUT1 is commanded to be pulled high, short is detected and outputs are Hi-Z. B
12, 13, 14, 15, 16, 17 GND Normal function. D
18, 19, 20 OUT2 If OUT2 is commanded to be pulled high, short is detected and outputs are Hi-Z. B
24 nSLEEP Both "S" & "P" variants: Device will be in SLEEP state and outputs are Hi-Z. B
VDD
25 IPROPI IPROPI feedback is lost. ITRIP regulation, if enabled, is also lost. B
26 nFAULT False fault signalling possible. Device will continue to operate as commanded. B
27 SDO SPI communication is lost. B
28 SDI SPI communication is lost. B
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin Description of Potential Failure Effect(s) Failure Effect Class
No. Name
1 SCLK SPI communication is lost. B
2 nSCS SPI communication is lost. B
3 PH/IN2 Normal function as register bit is used for direction control. D
4 EN/IN1 Load will be in re-circulation (braking). No risk of spin direction reversal. B
5 DRVOFF Pin based shutoff is triggered and outputs are Hi-Z. B
6, 7, 8, 21, 22, 23 VM Device is powered off with driver Hi-Z. B
9, 10, 11 OUT1 Load drive capability is lost. B
12, 13, 14, 15, 16, 17 GND Device is powered off with driver Hi-Z. B
18, 19, 20 OUT2 Load drive capability is lost. B
24 nSLEEP Both "S" & "P" variants: Device will be in SLEEP state and outputs are Hi-Z. B
VDD
25 IPROPI IPROPI feedback is lost. Load will be forced to recirculate if ITRIP regulation is enabled. B
26 nFAULT False fault signaling possible. Device will continue to operate as commanded. B
27 SDO SPI communication is lost. B
28 SDI SPI communication is lost. B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Short between pins Description of Potential Failure Effect(s) Failure Effect Class
SCLK SDI SPI communication is lost. B
nSCS SCLK SPI communication is lost. B
PH/IN2 nSCS Normal function as register bit is used for direction control. D
EN/IN1 PH/IN2 External PWM control is lost. Internal ITRIP regulation is OK. No risk of spin direction reversal. D
DRVOFF EN/IN1 Outputs are either Hi-Z or load is in re-circulation state. B
VM DRVOFF Outputs are Hi-Z. B
OUT1 VM If OUT1 is commanded to be pulled low, short is detected and outputs are Hi-Z B
GND OUT1 If OUT1 is commanded to be pulled high, short is detected and outputs are Hi-Z. B
OUT2 GND If OUT2 is commanded to be pulled high, short is detected and outputs are Hi-Z. B
VM OUT2 If OUT2 is commanded to be pulled low, short is detected and outputs are Hi-Z. B
nSLEEP VM "S" variant: SLEEP functionality is lost B
VDD "P" variant: Device damage possible. Device behavior can not be guaranteed. A
IPROPI nSLEEP "S" variant: IPROPI feedback is inaccurate. ITRIP regulation levels, if enabled, will be lower. B
VDD "P" variant: IPROPI feedback is inaccurate. Outputs are Hi-Z if ITRIP regulation is enabled.
nFAULT IPROPI False fault signaling possible. IPROPI feedback is inaccurate. ITRIP regulation levels, if enabled, will be lower. B
SDO nFAULT False fault signaling possible. SPI communication will be affected during fault assertion. B
SDI SDO SPI communication is lost. B
Table 4-5 Pin FMA for Device Pins Short-Circuited to supply VM
Pin Description of Potential Failure Effect(s) Failure Effect Class
No. Name
1 SCLK Device damage possible. A
2 nSCS Device damage possible. A
3 PH/IN2 Device damage possible. A
4 EN/IN1 Device damage possible. A
5 DRVOFF Outputs are Hi-Z. B
6, 7, 8, 21, 22, 23 VM Normal function. D
9, 10, 11 OUT1 If OUT1 is commanded to be pulled low, short is detected and outputs are Hi-Z. B
12, 13, 14, 15, 16, 17 GND Device is powered off with driver Hi-Z. B
18, 19, 20 OUT2 If OUT2 is commanded to be pulled low, short is detected and outputs are Hi-Z. B
24 nSLEEP "S" variant: SLEEP functionality is lost. B
VDD "P" variant: Device damage possible. A
25 IPROPI Device damage possible. A
26 nFAULT Device damage possible. A
27 SDO Device damage possible. A
28 SDI Device damage possible. A