SDAA226 March   2026 AM13E23019

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1AM13E230x Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of STM32G474x and AM13E230x MCUs
  5. 2Device Pinout Comparison
    1. 2.1 Device Pin and Signal Comparison Tables
      1. 2.1.1 Device Pin-to-Pin Comparison
      2. 2.1.2 STM32G474x Alternate Functions and AM13E230x Signal Names
      3. 2.1.3 STM32G474x Additional Functions and AM13E230x Analog Functions
    2. 2.2 Device Pinout Comparison by Package Type
    3. 2.3 Block Diagram Comparison of STM32G474x and AM13E230x
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 Operating Modes Summary and Comparison
    6. 3.6 Interrupt and Events Comparison
    7. 3.7 Debug and Programming Comparison
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO)
    2. 4.2 Serial Communications Peripherals
      1. 4.2.1 Universal Asynchronous Receiver-Transmitter (UART)
      2. 4.2.2 Serial Peripheral Interface (SPI)
      3. 4.2.3 Inter-Integrated Circuit (I2C)
    3. 4.3 Timers
    4. 4.4 Windowed Watchdog Timer (WWDT)
    5. 4.5 Controller Area Network (CAN)
  8. 5Analog Peripherals Comparison
    1. 5.1 Analog to Digital Converter (ADC)
    2. 5.2 Comparator Subsystem (CMPSS)
    3. 5.3 Digital to Analog Converter (DAC)
    4. 5.4 Programmable Gain Amplifier (PGA)
  9. 6System-Level Migration
    1. 6.1 Power, Clock, Reset Migration
    2. 6.2 Boot ROM Configured Pins
    3. 6.3 Additional Considerations

Serial Peripheral Interface (SPI)

Table 4-4 SPI Feature Set Comparison
Feature STM32G474x SPI AM13E230x UNICOMM SPI
Controller or peripheral operation Yes Yes
DMA Access Yes Yes
TX/RX FIFO Depth 4 entries 16 entries
Supported SPI Formats Motorola SPI, Texas Instruments, I2S Motorola SPI or Texas Instruments
Data Bit Width (Controller mode) 4 to 16 bits 4 to 16 bits
Data Bit Width (Peripheral mode) 4 to 16 bits 7 to 16 bits
Maximum Speed 75 Mbits/s in controller and up to 41 Mbits/s in peripheral mode 50 Mbits/s
Multi-controller Support Yes (Multi-controller via bus arbitration) No
Full-duplex Transfers Yes Yes
Half-duplex Transfer (bidirectional data line) Yes No
Simplex Transfer (unidirectional data line) Yes No
Hardware Chip Select Management Yes (NSS hardware mode support) Yes
Programmable Clock Polarity and Phase Yes (CPOL and CPHA) Yes (CTL0.SPO and CTL0.SPH bit)

Programmable Data Order (MSB first or LSB first)

Yes Yes
Hardware CRC Yes (polynomial configurable) No