SDAA206 March   2026 TAS2781

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 Typical Application Block Diagrams
    2. 2.2 Typical Schematics
      1. 2.2.1 External PVDDH Mode
      2. 2.2.2 Class-H Boosted Mode
      3. 2.2.3 TAS278X Power Modes
      4. 2.2.4 TAS278X Operational Modes
    3. 2.3 Layout Best Practices
      1. 2.3.1  DREG
      2. 2.3.2  IOVDD and IOVDD-SDW
      3. 2.3.3  AVDD
      4. 2.3.4  PVDDH
      5. 2.3.5  PVDDL
      6. 2.3.6  Class-D Outputs (OUTP and OUTN)
      7. 2.3.7  VSNSP and VSNSN
      8. 2.3.8  BSTP and BSTN
      9. 2.3.9  Ground Pins
      10. 2.3.10 Non-Soundwire Digital IO
      11. 2.3.11 Soundwire IO
  6. 3PCB Layers
  7. 4Summary
  8. 5References

2.3.4 PVDDH

Pin 28, PVDDH, is the high voltage class-D supply. High parasitic inductance between the PVDDH decoupling capacitor and the device pin can cause THD+N to degrade or device stability issues. the low ESL 0.1uF capacitor should be placed as close to the device pin as possible. And the bulk 10uF capacitors should be placed as close to the low ESL capacitor as possible. Use a wide polygon or trace to provide the PVDDH to the device pin. In the layout the ground side of the PVDDH decoupling capacitors should return to the pin 2 PGND Pin on the top layer. In systems where this is not feasible a ground polygon should be used on the top layer with many vias to the layer 2 GND. It is critical that the ground return path to pin2 is short and low inductance. The parasitic inductance seen by the PVDDH pin should not exceed 100 pH.

PVDDHFigure 2-8 PVDDH