SDAA206 March   2026 TAS2781

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 Typical Application Block Diagrams
    2. 2.2 Typical Schematics
      1. 2.2.1 External PVDDH Mode
      2. 2.2.2 Class-H Boosted Mode
      3. 2.2.3 TAS278X Power Modes
      4. 2.2.4 TAS278X Operational Modes
    3. 2.3 Layout Best Practices
      1. 2.3.1  DREG
      2. 2.3.2  IOVDD and IOVDD-SDW
      3. 2.3.3  AVDD
      4. 2.3.4  PVDDH
      5. 2.3.5  PVDDL
      6. 2.3.6  Class-D Outputs (OUTP and OUTN)
      7. 2.3.7  VSNSP and VSNSN
      8. 2.3.8  BSTP and BSTN
      9. 2.3.9  Ground Pins
      10. 2.3.10 Non-Soundwire Digital IO
      11. 2.3.11 Soundwire IO
  6. 3PCB Layers
  7. 4Summary
  8. 5References

2.3.11 Soundwire IO

Control the characteristic impedance of all the Soundwire signals to 50 ohms. Length match all bus segments between Host and device, as well as segments daisy chaining between device and device. Avoid routing any of these signals near any high current or switching signals, such as PVDDH, PVDDL, OUTP, OUTN, BSTP, BSTN, VSNSP, VSNSN. Avoid long un-terminated trace segments on the Soundwire Signals.
SoundwireFigure 2-15 Soundwire