SDAA199 December   2025 AM620-Q1 , AM625 , AM625-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Software Architecture
  6. 3 Sound Card Information
  7. 4 McASP - External Signals
  8. 5 MCASP Clock Generation and Configurations
  9. 6 Dummy Sound Card DTS Changes
  10. 7 Single DAI Link or a Single Sound Card
  11. 8 Multiple DAI Links - Single Card but Multiple Sub-Devices
  12. 9 MCASP - Practical Examples
  13. 10McASP as a Receiver
    1. 10.1 ADC or Codec as Clock Master
    2. 10.2 Device Tree Changes - Codec as Master and MCASP as Slave
  14. 11MCASP as Transmitter
    1. 11.1 Device Tree Changes - With Codec as Slave and MCASP as Master
  15. 12References

5 MCASP Clock Generation and Configurations

In some cases, MCASP is required to act as clock master and must generate clocks.

The following figure is a simplified block diagram of MCASP's clock generation architecture. For more detail, see the device-specific TRM.

MCASP Clock Generation Architecture Figure 5-1 MCASP Clock Generation Architecture

The block marked AUXCLK in Figure 2 is a clock source that is available to both the Rx and Tx sections of McASP. The source of AUXCLK varies, depending on the device, but it is often derived directly from the device’s main system clock source (usually an on-board oscillator or an externally generated square wave).

For both the receive and transmit sections, the AUXCLK is fed into an integer high-frequency clock divider: AHCLKRDIV or AHCLKXDIV. This clock signal can be divided down to generate the McASP’s Rx or Tx master clock: AHCLKR or AHCLKX. This signal can be driven out on its corresponding pin, if configured to do so. It also feeds the next clock divider: ACLKRDIV or ACLKXDIV. Similarly, the integer bit clock divider ACLK[R/X]DIV generates the McASP’s bit clock: ACLKR or ACLKX. That signal can be driven out on the corresponding pin. Note that the bit clock divider can instead be fed by the AHCLK[R/X] pin. The next stage of clock generation looks similar. These are the receive and transmit Frame Sync Generators (FSGs). The output of the FSGs will be AFSR and AFSX. These can also be driven out of their corresponding clock pins. The frame sync generator can be fed by an external bit clock provided to the ACLK[R/X] pin. This is not common, as the bit clock and frame sync are usually both internally generated, or both externally sourced.

A key point about the McASP’s clock generation architecture is that McASP has integer dividers (and frame sync generators) that can be used to generate internal clocks, and those internal clocks may be driven out of their corresponding device pins.