SDAA184 June   2026 TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Stage Overview
  6. 3Software Overview
    1. 3.1 Software Architecture
      1. 3.1.1 Devcie Initialization
        1. 3.1.1.1 Analog Peripherals Initialization
        2. 3.1.1.2 Control Peripherals Intialization
          1. 3.1.1.2.1 EPWM Initialization
          2. 3.1.1.2.2 CLB Initialization
        3. 3.1.1.3 System Peripherals Initialization
      2. 3.1.2 Interrupt Structure
    2. 3.2 PowerSuite Usage
  7. 4Lab Structure
    1. 4.1 Hardware Setup
    2. 4.2 Lab1
    3. 4.3 Lab2
    4. 4.4 Lab3
    5. 4.5 Lab4
  8. 5Summary
3.1.1.2.2 CLB Initialization

In this application, the Configurable Logic Block (CLB) modules are utilized to generate asynchronous events required for precise PWM control and diagnostics. Two CLB instances are employed AHB_CLB and ZVS_CLB each serving a distinct functional purpose within the system.

AHB_CLB

The AHB_CLB module is primarily responsible for generating the T1 and T2 events, which are crucial for light-load PWM waveform generation. These events define the timing boundaries within each PWM cycle, enabling controlled freewheeling intervals and adaptive switching behavior. This module uses the CLB1 instance configured on TILE0, as illustrated in Figure X. It utilizes seven input signals and implements three counter modules within the CLB fabric to synthesize precise timing events for T1 and T2 generation. The CLB outputs are routed to both the EPWM X-BAR and other CLB modules, where they serve as triggers for corresponding actions such as PWM edge control or timing synchronization.

AHB_CLB ConfigurationFigure 3-16 AHB_CLB Configuration.

ZVS_CLB

The ZVS_CLB module is used to monitor ZVS operation and assist with diagnostic event generation. It ensures that PWM transitions occur under Zero Voltage Switching conditions and provides feedback to the control loop for corrective actions when deviations occur. This logic is implemented using the CLB2 instance, configured on TILE1, as shown in Figure Y. It utilizes six input signals and employs two look-up tables (LUTs) that act as programmable combinational logic blocks. These LUT outputs are further processed through counter modules, and the final CLB outputs are routed via the CLBOUTPUT X-BAR and other CLB instances to create timing events and trigger diagnostics as needed.

ZVS_CLB ConfigurationFigure 3-17 ZVS_CLB Configuration.

The combined use of AHB_CLB and ZVS_CLB allows the firmware to flexibly generate and manage asynchronous events in hardware, significantly offloading the CPU. By integrating with the EPWM and X-BAR subsystems, these CLBs enable deterministic timing, low-latency event generation, and enhanced real-time responsiveness—critical for achieving high-efficiency, adaptive PWM control.