ZHCSGG0B February   2017  – July 2017 DAC38RF86 , DAC38RF87 , DAC38RF96 , DAC38RF97

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - DC Specifications
    6. 7.6  Electrical Characteristics - Digital Specifications
    7. 7.7  Electrical Characteristics - AC Specifications
    8. 7.8  PLL/VCO Electrical Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics, DAC38RF86 and DAC38RF96
      1. 7.10.1 Typical Characteristics, DAC38RF87 and DAC38RF97
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  SerDes Inputs
      2. 8.3.2  SerDes Rate
      3. 8.3.3  SerDes PLL
      4. 8.3.4  SerDes Equalizer
      5. 8.3.5  JESD204B Descrambler
      6. 8.3.6  JESD204B Frame Assembly
      7. 8.3.7  SYNC Interface
      8. 8.3.8  Single or Dual Link Configuration
      9. 8.3.9  Multi-Device Synchronization
      10. 8.3.10 SYSREF Capture Circuit
      11. 8.3.11 JESD204B Subclass 0 support
      12. 8.3.12 SerDes Test Modes through Serial Programming
      13. 8.3.13 SerDes Test Modes through IEEE 1500 Programming
      14. 8.3.14 Error Counter
      15. 8.3.15 Eye Scan
      16. 8.3.16 JESD204B Pattern Test
      17. 8.3.17 Multiband DUC (multi-DUC)
        1. 8.3.17.1 Multi-DUC input
        2. 8.3.17.2 Interpolation Filters
        3. 8.3.17.3 JESD204B Modes, Interpolation and Clock phase Programming
        4. 8.3.17.4 Digital Quadrature Modulator
        5. 8.3.17.5 Low Power Coarse Resolution Mixing Modes
        6. 8.3.17.6 Inverse Sinc Filter
        7. 8.3.17.7 Summation Block for Dual DUC Modes
      18. 8.3.18 PA Protection Block
      19. 8.3.19 Gain Block
      20. 8.3.20 Output Summation
      21. 8.3.21 Output Delay
      22. 8.3.22 Polarity Inversion
      23. 8.3.23 Temperature Sensor
      24. 8.3.24 Alarm Monitoring
      25. 8.3.25 Differential Clock Inputs
      26. 8.3.26 CMOS Digital Inputs
      27. 8.3.27 DAC Fullscale Output Current
      28. 8.3.28 Current Steering DAC Architecture
      29. 8.3.29 DAC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clocking Modes
      2. 8.4.2 PLL Bypass Mode Programming
      3. 8.4.3 Internal PLL/VCO
      4. 8.4.4 CLKOUT
      5. 8.4.5 Serial Peripheral Interface (SPI)
        1. 8.4.5.1 NORMAL (RW)
        2. 8.4.5.2 WRITE_TO_CLEAR (W0C)
    5. 8.5 Register Maps
      1. 8.5.1  Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
      2. 8.5.2  IO Configuration Register (address = 0x01) [reset = 0x1800]
      3. 8.5.3  Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
      4. 8.5.4  Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
      5. 8.5.5  SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = 0x0000]
      6. 8.5.6  SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = 0x0000]
      7. 8.5.7  Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
      8. 8.5.8  Page Set Register (address = 0x09) [reset = 0x0000]
      9. 8.5.9  SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
      10. 8.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
      11. 8.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
      12. 8.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0008]]
      13. 8.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
      14. 8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
      15. 8.5.15 JESD FIFO Control Register (address = 0x0D) [reset = 0x1300]
      16. 8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
      17. 8.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
      18. 8.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
      19. 8.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
      20. 8.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
      21. 8.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
      22. 8.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
      23. 8.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
      24. 8.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
      25. 8.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
      26. 8.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
      27. 8.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
      28. 8.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
      29. 8.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
      30. 8.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
      31. 8.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
      32. 8.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
      33. 8.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
      34. 8.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
      35. 8.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
      36. 8.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
      37. 8.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
      38. 8.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
      39. 8.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0000]
      40. 8.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0000]
      41. 8.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
      42. 8.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
      43. 8.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
      44. 8.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
      45. 8.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
      46. 8.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
      47. 8.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
      48. 8.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
      49. 8.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
      50. 8.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
      51. 8.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
      52. 8.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
      53. 8.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
      54. 8.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
      55. 8.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
      56. 8.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
      57. 8.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
      58. 8.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
      59. 8.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
      60. 8.5.60 JESD Alarms for Lane 1 Register (address = 0x65 01100101) [reset = 0x0000]
      61. 8.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
      62. 8.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
      63. 8.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
      64. 8.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
      65. 8.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
      66. 8.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
      67. 8.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
      68. 8.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
      69. 8.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xF000]
      70. 8.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
      71. 8.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x8000]
      72. 8.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
      73. 8.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
      74. 8.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
      75. 8.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
      76. 8.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
      77. 8.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
      78. 8.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
      79. 8.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
      80. 8.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
      81. 8.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
      82. 8.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
      83. 8.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
      84. 8.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x0002]
      85. 8.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
      86. 8.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
      87. 8.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
      88. 8.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
      89. 8.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-up Sequence
    2. 9.2 Typical Application: Multi-band Radio Frequency Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Calculating the JESD204B SerDes Rate
        2. 9.2.2.2 Calculating valid JESD204B SYSREF Frequency
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 特性

  • 14 位分辨率
  • 最大 DAC 采样率：
    • 9.0GSPS（DAC38RF86、DAC38RF96）
    • 6.2GSPS（DAC38RF87、DAC38RF97）
  • 主要规格：
    • 2.1GHz 时的射频满量程输出功率：0dBm
    • 频谱性能，DAC38RF87/97
      • fDAC = 5898.24MSPS，fOUT = 2.14GHz
        • WCDMA ACLR：73dBc
        • WCDMA 备选 ACLR：77dBc
    • 频谱性能，DAC38RF86/96
      • fDAC = 8847.36MSPS，fOUT = 3.7GHz
        • 20MHz LTE ACLR：66dBc
      • fDAC = 9GSPS，fOUT = 1.8GHz，–6dBFS
        • IMD3 = 70dBc（10MHz 音调间隔）
  • 每个 DAC 配有双频带数字上变频器
    • 6、8、10、12、16、18、20 或 24 倍插值运算
    • 分辨率为 48 位的 4 个独立 NCO
  • JESD204B 接口，子类 1
    • 支持多芯片同步
    • 最高通道速率：12.5Gbps
  • 具有集成巴伦的单端输出 覆盖 700MHz 至 3800MHz
  • 内部 PLL 和 VCO
    • DAC38RF86/96：fC(VCO) = 8.85GHz
    • DAC38RF87/97：fC(VCO) = 5.90GHz
  • 功耗：每通道 1.4W 至 2.2W
  • 电源：–1.8V、1V、1.8V
  • 封装：10mm x 10mm BGA，间距为 0.8mm，具有 144 个焊球

2 应用

  • 无线通信
  • 通信测试设备
  • 任意波形发生器
  • 军用软件定义的无线电
  • 雷达和卫星通信 (SATCOM)

3 说明

DAC38RF86/96 是一款高性能、双通道/通道、14 位、9GSPS、射频采样数模转换器 (DAC)，能够合成 0GHz 至 4.5GHz 范围内的宽带信号。DAC38RF87/97 也是一款高性能、双通道、14 位、6GSPS、射频采样数模转换器 (DAC)，能够合成 0GHz 至 3GHz 范围内的宽带信号。高动态范围允许 DAC38RFxx 系列为各种 应用 生成信号，包括用于无线基站和雷达的 3G/4G 信号。

该器件具有一个低功耗 JESD204B 接口，其通道多达 8 条，最高位率为 12.5Gbps/通道，复合输入数据速率为 1.25GSPS/通道。DAC38RFxx 为每个通道提供两个数字上变频器，具有多种内插速率选项。具有频率灵活的独立 NCO 的数字正交调制器可用于支持多频段操作。集成了兼容 GSM 的低相位噪声 PLL/VCO，可通过允许使用频率较低的参考时钟来简化 DAC 采样时钟的生成

器件信息(1)

器件型号 输出类型 通道数量
DAC38RF86 单端 2
DAC38RF96
DAC38RF87
DAC38RF97
  1. 如需了解所有可用器件选项，请参阅器件比较表。

1.84GHz 和 2.14GHz 下的 2 x 20MHz LTE，
展频为 800MHz

DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97 spectrum_B1_B3_SLASEA3.gif

4 修订历史记录

Changes from A Revision (April 2017) to B Revision

  • 已更改 说明Go
  • 更改了器件信息表Go
  • Changed From: alarm_out_pol To: alm_out_pol in ALARM pin description in the Pin Functions tableGo
  • Changed the Description of pins A3, A4, A7, A6, A9, A10, A12, F11, F7, G6, G12, H5, H7, J6, J11 in the Pin Functions tableGo
  • Added description to TXENABLE pin in the Pin Functions tableGo
  • Changed the MAX value of VEE18N rail in the Absolute Maximum Ratings From: 0.5 V To: 0.3 VGo
  • Added "Supply Voltage Range" to the Recommended Operating Conditions tableGo
  • Added "Reference voltage drift" to the Electrical Characteristics - DC Specifications tableGo
  • Added Isolation vs Output Frequency plot in Figure 14Go
  • Added Isolation vs output frequency plot for DAC38RF87/97 in Figure 30 Go
  • Changed the MPY values in Table 4Go
  • Added MPY value for 16.5x to Table 4Go
  • Changed x To: √ in the JESD204B Formats for DAC38RFxx tableGo
  • Changed JESD204B frame format for LMFSHd=84111 in Table 12Go
  • Changed JESD204B frame format for LMFSHd=44210 in Table 14Go
  • Changed JESD204B frame format for LMFSHd=24410 in Table 16Go
  • Changed JESD204B frame format for LMFSHd=44210 in Table 17Go
  • Changed JESD204B frame format for LMFSHd=88210 in Table 18Go
  • Changed JESD204B frame format for LMFSHd=24410 in Table 19Go
  • Changed JESD204B frame format for LMFSHd=48410 in Table 20Go
  • Changed JESD204B frame format for LMFSHd=24310 in Table 21Go
  • Changed JESD204B frame format for LMFSHd=48310 in Table 22Go
  • Changed Table 33Go
  • Changed register field programming values for LMFSHd=24410 and 24310 in Table 36Go
  • Changed the bit positions of N_M1 register field in Table 37 Go
  • Changed the bit positions of N_M1' N_M1’ (NPRIME_M1) register field in Table 37 Go
  • Deleted ISFIRCD_ENA and ISFIR_AB regsiter fields. Added ISFIR_ENA register field in Inverse Sinc FilterGo
  • Changed the description of DAC PLL alarm in Alarm MonitoringGo
  • Changed from BIST_ENA to Reserved in Table 56 Go
  • Changed from BIST_ZERO to Reserved in Table 56 Go
  • Changed the description of OUTSUM_SEL field in Table 64 Go
  • Changed the junction temp and loop filter voltage range for PLL tuning in Figure 150 Go

Changes from * Revision (February 2017) to A Revision

  • 将标题从“双通道或单通道、单端、14位、9GSPS...”更改为“双通道、单端、14 位、6GSPS 和 9GSPS...”Go
  • Changed the Description of SYSREF+ From: "LVPECL SYSREF positive input." To: "LVPECL SYSREF positive input, self biased." in the Pin Functions tableGo
  • Deleted Latency and PLL/VCO parameters from the end of the Electrical Characteristics - DC Specifications tableGo
  • Changed the Electrical Characteristics - AC Specifications table, and added "0 dBFS" amplitude of input digital data in test conditionsGo
  • Added the PLL/VCO Electrical Characteristics tableGo
  • Added JESD204B clock phase register setting to Table 36 Go
  • Removed descriptions for CLKJESD_DIV register from Table 36 Go
  • Added JESD204B clock phase register setting to Table 37 Go
  • Added information about the DAC output total current for various full scale current settings in DAC Fullscale Output Current Go
  • Changed Table 125 Go
  • Changed description of SERDES_REFCLK_DIV register field in Table 126 Go
  • Changed Bit 12:11, 6:5 and 4:2 of Table 129 Go