ZHCSNG6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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Calculation of ZVS Sensing Network

There are three components in the application circuit to help the depletion MOSFET (QS) perform ZVS sensing safely: CSWS, RSWS, and DSWS. Design considerations and selection guidelines for the values of these components are given here.

At the rising edge of the switch-node voltage, the fast dV/dt may couple through the drain-to-source capacitance of QS (COSS(Qs)) and generate a charge current that flows into the circuit loading on the QS source pin. The result may be a possible voltage overshoot on both the SWS pin and across the gate-to-source of QS (VGS(Qs)) because the gate is tied to P13. The SWS pin, having an absolute maximum voltage rating of 38 V, can handle higher voltage stress than VGS(Qs). Therefore, carefully select a capacitor (CSWS) between the SWS pin and GND to prevent the voltage overshoot from damaging the QS gate. Because COSS(Qs) and CSWS form a voltage divider, the minimum CSWS (CSWS(min)) can be derived as

Equation 36. C S W S m i n = C O S S Q s × V B U L K M A X + N P S V O + V F V P 13 + V G S M A X Q s

where

  • VGS_MAX(Qs) is the de-rated maximum gate-to-source voltage of QS
  • VP13 is the steady-state voltage level of 13 V

Without resistive damping, both the charge current on the rising edge of VSW and the discharge current on the falling edge of VSW may oscillate with the parasitic series inductance within the ZVS sensing network resonating with CSWS. Therefore, a series resistor (RSWS) between SWS pin and source-pin of QS is used to dampen any high-frequency ringing, helping to obtain a cleaner sensing signal on the SWS pin and preventing any high-frequency current from interfering with other noise-sensitive signals. RSWS can be expressed as:

Equation 37. GUID-4E696F55-453C-497E-B8E4-968F250CE6ED-low.gif

where

  • LSWS is the lumped parasitic inductance including the packaging of QS and PCB traces of QS and CSWS return path
  • CDz is the junction capacitance of any zener diode applied across CSWS, if used (usually not necessary).

For most applications, use a resistor value slightly higher than 500 Ω. The resistor and a 22-pF ceramic capacitor between the SWS pin and the bulk input capacitor ground form a small sensing delay to help the internal detection circuit to identify the ZVS characteristic correctly.

Based on the above design guide, even though RSWS and CSWS may be sufficient to manage the voltage overshoot in normal operation, a low-capacitance bi-directional TVS diode (DSWS) across BSS126 gate and source is highly recommended to serve as a safety backup of the ZVS sensing network. Regular Zener diodes are not suitable due to high capacitance and slow clamping response. Ensure the clamping voltage of DSWS is less than BSS126 voltage rating but greater than 15 V.

A general recommendation is to use a 50-V 22-pF C0G-type ceramic capacitor for CSWS, a 510-Ω chip resistor for RSWS, and a bi-directional TVS diode with clamp voltage of 18 V for DSWS. Too large of RSWS or CSWS introduces a sensing delay between the actual VSW and the SWS pin, causing the ZVS control to unnecessarily extend tDM in order to pull down VSW earlier than expected before the end of tZ . As shown in Figure 7-5, the larger RSWS is, the smaller supply current to charge the VDD capacitor. If the reduced charge current (ISWS) is lower than the total consumed current from the controller (ISTART) and from the external circuitry on the VDD and P13 pins, VVDD may not be able to reach VVDD(ON) and the controller can not initiate any switching event.