ZHCSHY7A April   2018  – May 2018 UCC28742

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      10W、5V 交流/直流转换器的典型效率
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 VS (Voltage-Sense)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CS (Current Sense)
        6. 7.3.1.6 FB (Feedback)
      2. 7.3.2 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      3. 7.3.3 Control Law
      4. 7.3.4 Constant Current Limit and Delayed Shutdown
      5. 7.3.5 Valley-Switching and Valley-Skipping
      6. 7.3.6 Start-Up Operation
      7. 7.3.7 Fault Protection
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  VDD Capacitance, CDD
        3. 8.2.2.3  VDD Start-Up Resistance, RSTR
        4. 8.2.2.4  Input Bulk Capacitance and Minimum Bulk Voltage
        5. 8.2.2.5  Transformer Turns Ratio, Inductance, Primary-Peak Current
        6. 8.2.2.6  Transformer Parameter Verification
        7. 8.2.2.7  VS Resistor Divider and Line Compensation
        8. 8.2.2.8  Standby Power Estimate
        9. 8.2.2.9  Output Capacitance
        10. 8.2.2.10 Feedback Loop Design Consideration
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 使用 WEBENCH® 工具创建定制设计
      2. 11.1.2 器件命名规则
        1. 11.1.2.1  电容术语（以法拉为单位）
        2. 11.1.2.2  占空比术语
        3. 11.1.2.3  频率术语（以赫兹为单位）
        4. 11.1.2.4  电流术语（以安培为单位）
        5. 11.1.2.5  电流和电压调节术语
        6. 11.1.2.6  变压器术语
        7. 11.1.2.7  功率术语（以瓦特为单位）
        8. 11.1.2.8  电阻术语（以 Ω 为单位）
        9. 11.1.2.9  时序术语（以秒为单位）
        10. 11.1.2.10 电压术语（以伏特为单位）
        11. 11.1.2.11 交流电压术语（以 VRMS 为单位）
        12. 11.1.2.12 效率术语
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.2 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation

Figure 9 shows a simplified flyback convertor with the main output-regulation blocks of the device shown, along with typical implementation of secondary-side-derived regulation. The power-train operation is the same as any DCM-flyback circuit. A feedback current is optically coupled to the controller from a shunt-regulator sensing the output voltage.

UCC28742 fig09_Vreg_blk_lusbf3_1.gifFigure 9. Simplified Flyback Converter
(with the Main Voltage Regulation Blocks)

In this configuration, a secondary-side shunt-regulator, such as the TL431 (or ATL431), generates a current through the input photo-diode of an optocoupler. The photo-transistor delivers a proportional current that is dependent on the current-transfer ratio (CTR) of the optocoupler to the FB input of the UCC28742 controller. This FB current then converts into the VCL by the input-mirror network, detailed in the device block diagram (see Functional Block Diagram). Output-voltage variations convert to FB-current variations. The FB-current variations modify the VCL which dictates the appropriate IPP and fSW necessary to maintain CV regulation. At the same time, the VS input senses the auxiliary winding voltage during the transfer of transformer energy to the secondary output to monitor for an output overvoltage condition. When fSW reaches the converter target maximum frequency (i.e., corresponding de-mag time duty reaches 0.475), Constant Current Limit is triggered and further increases in VCL cannot increase fSW anymore. (see Figure 10, Control Law and Constant Current Limit and Delayed Shutdown)

UCC28742 fig10_from_fig13_lusca8.gifFigure 10. Auxiliary Winding Voltage

The UCC28742 samples the VS input voltage at the end of demagnetization time for output overvoltage detection and to determine the total demagnetization time for output current control in Constant Current Limit operation.

In order to maintain best performance of these functions the reset time and ringing of the auxiliary winding voltage should meet certain guidelines. Referring to Figure 11, the width of the leakage spike at the VS input should be less than tDM_BLANK. Minimum tDM_BLANK is 3 µs at maximum peak priamry current levels and proportionally less at lower peak primary current levels (the lowest 0.75 µs should be observed at high line and no load condition). In addition, any ringing following the spike should be reduced to < 160 mVpp (scaled to the VS pin) 200 ns before the end of the demagnetization time.

As mentioned in Device Functional Modes, when IPP < IPP(max), the device operation enters a “Wait” state during each switching cycle of its non-switching portion as shown in Figure 11. In the Wait state, the device bias current changes to IWAIT (typical 80 µA) from IRUN (typical 1.8 mA), reducing its bias power to help boost efficiency at light load and to reduce no-load input power.

UCC28742 fig11.gifFigure 11. Auxiliary Waveform Details