SLUSFS4A September   2025  – September 2025 UCC27734-Q1 , UCC27735-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Dynamic Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Enable Function (UCC277x5-Q1 Only)
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Output Stage
      6. 6.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 6.3.7 HS Node dV/dt
      8. 6.3.8 Split Grounds (COM and VSS)
      9. 6.3.9 Operation Under Negative HS Voltage Condition
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input and Output Logic Table
      2. 6.4.2 Operation Under 100% Duty Cycle Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 7.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 7.2.2.3 Selecting VDD Bypass Capacitor (CVDD)
        4. 7.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 7.2.2.5 Selecting Gate Resistor RHO/RLO
        6. 7.2.2.6 Selecting Bootstrap Diode
        7. 7.2.2.7 Estimate the UCC2773x-Q1 Power Losses
        8. 7.2.2.8 Application Example Schematic Note
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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5.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to COM (unless otherwise noted), currents are positive into and negative out of the specified terminal.(1)(2)
PARAMETER MIN MAX UNIT
Input voltage HI, LI, EN (3) with respect to VSS –6 23 V
VDD Supply Voltage –0.3 23
VDD-VSS -0.3 23
HB –0.3 700
HB–HS –0.3 23
Output voltage HO DC HS–0.3 HB+0.3 V
Transient, less than 100 ns(4) HS–2 HB+0.3
LO DC –0.3 VDD+0.3 V
Transient, less than 100 ns(4) –2 VDD+0.3
HS–VSS HS DC –18(5) 700 V
Transient, less than 100 ns(4) –23(5) 700 V
VSS–COM VSS–COM UCC27735-Q1 only –7 6 V
dVHS/dt Allowable offset supply voltage transient  –200 200 V/ns
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3) The maximum voltage on the input pins is not restricted by the voltage on the VDD pin.
(4) Values are verified by characterization on bench.
(5) At HB–HS = 15 V.