SLUSFS4A September   2025  – September 2025 UCC27734-Q1 , UCC27735-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Dynamic Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Enable Function (UCC277x5-Q1 Only)
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Output Stage
      6. 6.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 6.3.7 HS Node dV/dt
      8. 6.3.8 Split Grounds (COM and VSS)
      9. 6.3.9 Operation Under Negative HS Voltage Condition
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input and Output Logic Table
      2. 6.4.2 Operation Under 100% Duty Cycle Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 7.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 7.2.2.3 Selecting VDD Bypass Capacitor (CVDD)
        4. 7.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 7.2.2.5 Selecting Gate Resistor RHO/RLO
        6. 7.2.2.6 Selecting Bootstrap Diode
        7. 7.2.2.7 Estimate the UCC2773x-Q1 Power Losses
        8. 7.2.2.8 Application Example Schematic Note
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

UCC27734-Q1 UCC27735-Q1 D Package 14-Pin SOIC Top ViewFigure 4-1 D Package 14-Pin SOIC Top View
UCC27734-Q1 UCC27735-Q1 D Package 8-Pin SOIC Top ViewFigure 4-2 D Package 8-Pin SOIC Top View
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME 14D 8D
HB 13 8 I High-side floating supply. Bypass this pin to HS with a suitable capacitor to sustain boot-strap circuit operation in the desired application, typically 10× bigger than gate capacitance.
HI 1 1 I Logic input for high-side driver. If HI is unbiased or floating, HO is held low.
EN/NC 4 – I Enable input for high-side and low-side driver. This pin biased low, disables both HO and LO regardless of HI and LI state, This pin biased high or floating enables both HO and LO.
HO 12 7 O High-side driver output.
HS 11 6 – Return for high-side floating supply.
LI 2 2 I Logic input for low-side driver. If LI is unbiased or floating, LO is held low.
LO 6 4 O Low-side driver output.
NC 8, 9, 10, 14 – – No connection.
VDD 7 5 I Bias supply input. Power supply for the input logic side of the device and also low-side driver output. Bypass this pin to VSS with typical 1µF SMD capacitor (typically CVDD needs to be 10 × CBOOT). If shunt resistor used between COM and VSS, then also bypass this pin to COM with a 100nF SMD capacitor
COM 5 3 – Return for low-side driver output. Internally tied to VSS in UCC27734-Q1.
VSS 3 – – Logic ground.