SLUSFZ6 September   2025 UCC218915-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Ratings
    6. 5.6 Insulation Specifications
    7. 5.7 Electrical Characteristics
    8. 5.8 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power Supplies
      2. 6.3.2  VCC and VDD Undervoltage Lockout (UVLO)
      3. 6.3.3  Input Filters for IN+, IN- and RST/EN
      4. 6.3.4  Pre-Driver Outputs
      5. 6.3.5  External Active Miller Clamp
      6. 6.3.6  Desaturation (DESAT) Protection
      7. 6.3.7  Soft Shutdown
      8. 6.3.8  Fault (FLT), Reset and Enable (RST/EN)
      9. 6.3.9  Active Short Circuit (ASC) Support and Feedback (ASC_FB)
      10. 6.3.10 Overtemperature Protection
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Filters for IN+, IN- and RST/EN
        2. 7.2.2.2 PWM Interlock of IN+ and IN-
        3. 7.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 7.2.2.4 RST/EN Pin Control
        5. 7.2.2.5 External Active Miller Clamp
        6. 7.2.2.6 Overcurrent and Short Circuit Protection
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Mechanical Data

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DFP|28
散热焊盘机械数据 (封装 | 引脚)

6.3.4 Pre-Driver Outputs

The output stage of the is designed to drive a complimentary pair of external buffer MOSFETs in a push-pull configuration. The PMOS driver (OUTP) and the NMOS driver (OUTN) can each source and sink 2.8A making it suitable for driving a wide range of buffer MOSFETs to cover a wide range of power levels. OUTP and OUTN are driven complimentary with a deadtime, tOUTDT, to prevent cross conduction. OUTP drives the gate of an external PMOS between VDD and VBP, which is an internally generated rail that is 11V below VDD. OUTN drives the gate of an external NMOS between VEE and VBN, which is an internally generated rail that is 11V above VEE. A simplified schematic of the pre-driver architecture is shown in Figure 6-4.

UCC218915-Q1 Pre-Driver Output Architecture Figure 6-4 Pre-Driver Output Architecture

Input-to-output states are given in Table 6-1 where ASC is not active and no system faults are present. A timing diagram showing the relationship betweein inputs and outputs is shown in Figure 6-5. Propagation delays from input-to-output, deadtime between OUTN and OUTP transitions, and rise and fall times of the output signals are shown.

Table 6-1 Input-to-Output States with ASC Not Active and No System Faults Present
RST/EN IN+ IN- OUTP OUTN STATE OF EXTERNAL BUFFER FETS STATE OF EXTERNAL POWER SWITCH
GND x x VDD VBN NMOS On Off
VCC GND x VDD VBN NMOS On Off
VCC VCC GND VBP VEE PMOS On On
VCC VCC VCC VDD VBN NOMS On Off
UCC218915-Q1 Input-to-Output Timing Diagram Figure 6-5 Input-to-Output Timing Diagram