ZHCSHS5B February   2018  – February 2024 UCC21222

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety-Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Thermal Derating Curves
    12. 5.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 6.1 Minimum Pulses
    2. 6.2 Propagation Delay and Pulse Width Distortion
    3. 6.3 Rising and Falling Time
    4. 6.4 Input and Disable Response Time
    5. 6.5 Programmable Dead Time
    6. 6.6 Power-Up UVLO Delay to OUTPUT
    7. 6.7 CMTI Testing
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21222
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open
        2. 7.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Designing INA/INB Input Filter
        3. 8.2.2.3 Select Dead Time Resistor and Capacitor
        4. 8.2.2.4 Select External Bootstrap Diode and its Series Resistor
        5. 8.2.2.5 Gate Driver Output Resistor
        6. 8.2.2.6 Estimating Gate Driver Power Loss
        7. 8.2.2.7 Estimating Junction Temperature
        8. 8.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.8.1 Selecting a VCCI Capacitor
          2. 8.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.8.3 Select a VDDB Capacitor
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement Considerations
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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特性

  • 可通过电阻器编程的死区时间
  • 通用:双路低侧、双路高侧或半桥驱动器
  • 4A 峰值拉电流和 6A 峰值灌电流输出
  • 输入 VCCI 范围为 3V 至 5.5V
  • 高达 18V 的 VDD 输出驱动电源
    • 8V VDD UVLO
  • 开关参数:
    • 28ns 典型传播延迟
    • 10ns 最小脉冲宽度
    • 5ns 最大延迟匹配
    • 5.5ns 最大脉宽失真
  • TTL 和 CMOS 兼容输入
  • 集成抗尖峰脉冲滤波器
  • I/O 承受 –2V 电压的时间达 200ns
  • 共模瞬态抗扰度 (CMTI) 大于 100V/ns
  • 隔离栅寿命 >40 年
  • 浪涌抗扰度高达 7800VPK
  • 窄体 SOIC-16 (D) 封装
  • 安全相关认证(计划):
    • 符合 DIN V VDE V 0884-11:2017-01 和 DIN EN 61010-1 标准的 4242VPK 隔离
    • 符合 UL 1577 标准且长达 1 分钟的 3000VRMS 隔离
    • 符合 IEC 60950-1、IEC 62368-1 和 IEC 61010-1 终端设备标准的 CSA 认证
    • 符合 GB4943.1-2011 的 CQC 认证
  • 使用 UCC21222 并借助 WEBENCH® Power Designer 创建定制设计