ZHCSH68F November   2017  – February 2024 UCC21220 , UCC21220A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Thermal Derating Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Minimum Pulses
    2. 7.2 Propagation Delay and Pulse Width Distortion
    3. 7.3 Rising and Falling Time
    4. 7.4 Input and Disable Response Time
    5. 7.5 Power-up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21220 and UCC21220A
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimating Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

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9.2.3 Application Curves

Figure 9-5 and Figure 9-6 shows the bench test waveforms for the design example shown in Figure 9-1 under these conditions: VCC = 5.0 V, VDD = 12 V, fSW = 100 kHz, VDC-Link = 400 V.

Channel 1 (Yellow): INA pin signal.

Channel 2 (Blue): INB pin signal.

Channel 3 (Pink): Gate-source signal on the high side power transistor.

Channel 4 (Green): Gate-source signal on the low side power transistor.

In Figure 9-5, INA and INB are sent complimentary 3.3-V, 20%/80% duty-cycle signals with 200ns deadtime. The gate drive signals on the power transistor have a 200-ns dead time with 400V high voltage on the DC-Link, shown in the measurement section of Figure 9-5. Note that with high voltage present, lower bandwidth differential probes are required, which limits the achievable accuracy of the measurement.

Figure 9-6 shows a zoomed-in version of the waveform of Figure 9-5, with measurements for propagation delay and deadtime. Importantly, the output waveform is measured between the power transistors’ gate and source pins, and is not measured directly from the driver's OUTA and OUTB pins.

GUID-227CFE9C-861F-48DD-A27C-08182F8743D6-low.gif
Figure 9-5 Bench Test Waveform for INA/B and OUTA/B
GUID-0CC8973A-34E1-4E9B-A181-06F91FD247F9-low.gif
Figure 9-6 Zoomed-In bench-test waveform