ZHCSQX4F August   1995  – August 2022 UC1823A , UC1825A , UC2823A , UC2823B , UC2825A , UC2825B , UC3823A , UC3823B , UC3825A , UC3825B

PRODUCTION DATA  

  1. 1特性
  2. 2说明
  3. 3Revision History
  4. 4Ordering Information
  5. 5Pin Configuration and Functions
    1.     Terminal Functions
  6. 6Specifications
    1. 6.1 ABSOLUTE MAXIMUM RATINGS
    2. 6.2 Thermal Information
    3. 6.3 ELECTRICAL CHARACTERISTICS
    4. 6.4 ELECTRICAL CHARACTERISTICS
  7. 7Application and Implementation
    1. 7.1 LEADING EDGE BLANKING
    2. 7.2 UVLO、软启动和故障管理
    3. 7.3 ACTIVE LOW OUTPUTS DURING UVLO
    4. 7.4 CONTROL METHODS
    5. 7.5 SYNCHRONIZATION
    6. 7.6 HIGH CURRENT OUTPUTS
    7. 7.7 GROUND PLANES
    8. 7.8 OPEN LOOP TEST CIRCUIT
  8. 8Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 术语表
  9. 9Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DW|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

Terminal Functions

TERMINAL I/O DESCRIPTION
NAME NO.
J, N, or DW Q or L
CLK/LEB 4 5 O Output of the internal oscillator
CT 6 8 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length.
EAOUT 3 4 O Output of the error amplifier for compensation
GND 10 13 Analog ground return pin
ILIM 9 12 I Input to the current limit comparator
INV 1 2 I Inverting input to the error amplifier
NI 2 3 I Non-inverting input to the error amplifier
OUTA 11 14 O High current totem pole output A of the on-chip drive stage.
OUTB 14 18 O High current totem pole output B of the on-chip drive stage.
PGND 12 15 Ground return pin for the output driver stage
RAMP 7 9 I Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input.
RT 5 7 I Timing resistor connection pin for oscillator frequency programming
SS 8 10 I Soft-start input pin which also doubles as the maximum duty cycle clamp.
VC 13 17 Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths.
VCC 15 19 Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths
VREF 16 20 O 5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane.