SLVSMG3 June   2026 TXG4122

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions—TXG4122
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics, VCCA = 3.3 ± 0.3V
    8. 5.8 Switching Characteristics, VCCA = 5 ± 0.5V
    9. 5.9 Typical Characteristics
  7. 6 AC Noise Tolerance
  8. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Level Translation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

  • Supply Voltage Selection
    • Set VCC1 to the supply of the Side 1 domain (3.0 to 5.5V) and VCC2 to the supply of the Side 2 domain (2.25V to 5.5V). These ranges are assymetric.
    • Pull-up resistors on each side must be connected to that side's VCC so that the logic-high level matches the local domain voltage.
  • Pull-up Resistor Selection (RP)
    • Side 1 and Side 2 have different sink current limits (IOL1 = 16.5mA, IOL2 = 30mA) and different maximum capacitive loads (C1 = 80pF, C2 = 550pF), so the pull-up resistor must be selected independently for each side.
    • For each side, verify that VCC / RP does not exceed the rated IOL and that the rise time meets the I2C specifications for the target bus speed.
  • Ground Offset Voltage
    • The DC offset between GND1 and GND2 must not exceed ±40V. For dynamic ground shifts, ensure dv/dt stays below the CMTI rating of 2kV/μs.
    • Ensure the supply voltage on each side does not exceed 5.5V above its local ground reference (VCC1 to GND1 ≤ 5.5V and VCC2 to GND2 ≤ 5.5V - per Recommended Operating Conditions). This constraint is independent of the ground offset between GND1 and GND2.