6.2.1 Design Requirements

Table 6-1 lists the design parameters for the typical application shown in Section 6.2.

6.2.2 Detailed Design Procedure

6.2.2.1 Upstream Port Implementation

Figure 6-3 shows how the upstream of the TUSB3410 device is connected to a USB-2.0 Type B connector. The VBUS of the USB-2.0 connector is connected to a 3.3-V voltage regulator, which generates the 3.3 V required for VCC. The 3.3 V generated by this voltage regulator will pass through a voltage divider to generate the 1.8 V that is required for VDD.

Figure 6-3 Upstream Port Implementation Schematic

6.2.2.2 Crystal Implementation

The TUSB3410 device requires a 12-MHz clock source to work properly, which is placed across the X1 and X2 terminals as shown in Figure 6-4.

TI recommends using a parallel-resonant crystal. Most parallel-resonant crystals are specified at a frequency with a load capacitance of 18 pF. This load can be realized by placing 33-pF capacitors from each end of the crystal to ground. Together with the input capacitance of the TUSB3410 device and stray board capacitance, this setup provides close to two 36-pF capacitors in series to emulate the 18-pF load requirement.

Figure 6-4 Crystal Implementation Schematic

6.2.2.3 RS-232 Implementation

All the serial data lines and serial control signals (DTR, RTS, SOUT/IR_SOUT, SIN/IR_SIN, RI/CP, DCD, DSR, and CTS) must go through an RS-232 driver (see Figure 6-5). For this example, the SN75LV4737A device is used (see SLLS178 for more details about the RS-232 driver). After the RS-232 driver is placed, the serial data lines and serial control signals are connected to a DB9 connector.

Figure 6-5 RS-232 Implementation Schematic

6.2.2.4 TUSB3410 Power Implementation

Figure 6-6 shows the power implementation for the TUSB3410 device.

Figure 6-6 Power Implementation

6.2.3 Application Performance Plot

Figure 6-7 High-Speed Upstream Port

6.3.1 Layout Guidelines

A primary concern when designing a system is accommodating and isolating high-speed signals. As highspeed signals are most likely to impact or be impacted by other signals, they must be laid out early (preferably first) in the PCB design process to ensure that prescribed routing rules can be followed. Table 6-2 outlines the signals requiring the most attention in a USB layout.

Use the following routing and placement guidelines when laying out a new design for the USB physical layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI) problems on a four-or-more layer evaluation module (EVM).

• Place the USB PHY and major components on the un-routed board first.
• Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.
• Route the high-speed USB signals on the plane closest to the ground plane, whenever possible.
• Route the high-speed USB signals using a minimum of vias and corners. This reduces signal reflections and impedance changes.
• When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
• Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
• Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then the stub should be less than 200 mils.
• Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing over anti-etch, commonly found with plane splits.

6.3.2 Differential Signal Spacing

To minimize crosstalk in USB implementations, the spacing between the signal pairs must be a minimum of 5 times the width of the trace. This spacing is the 5W rule. Also, maintain a minimum keep-out area of 30 mils to any other signal throughout the length of the trace. Where the USB differential pair abuts a clock or a periodic signal, increase this keep-out to a minimum of 50 mils to ensure proper isolation. Figure 6-8 shows an example of USB2 differential signal spacing.

Figure 6-8 USB2 Differential Signal Spacing (mils)

6.3.3 Differential Signal Rules

• Do not place probe or test points on any USB differential signal.
• Do not route USB traces under or near crystals, oscillators, clock signal generators, switching power regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals.
• After BGA breakout, keep USB differential signals clear of the SoC because high current transients produced during internal state transitions can be difficult to filter out.
• When possible, route the USB differential pair signals on the top or bottom layer of the PCB with an adjacent GND layer. TI does not recommend stripline routing of the USB differential signals.
• Ensure that USB differential signals are routed ≥ 90 mils from the edge of the reference plane.
• Ensure that USB differential signals are routed at least 1.5 W (calculated trace-width × 1.5) away from voids in the reference plane. This rule does not apply where SMD pads on the USB differential signals are voided.
• Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the transmission lines.
• Maximize differential pair-to-pair spacing when possible.

For specific USB-2.0 layout guidelines, refer to USB Layout Guidelines (SPRAAR7).

6.3.4 Layout Example

Figure 6-9 Layout Example for TUSB3410

6.4.1 Digital Supplies 3.3 V

The TUSB3410 requires a 3.3-V digital power source.

The 3.3-V terminals are named VCC and supply power to most of the input and output cells. VCC supplies must have 0.1-μF bypass capacitors to VSS (ground) to ensure proper operation. One capacitor per power terminal is sufficient and should be placed as close to the terminal as possible to minimize trace length. TI also recommends smaller value capacitors like 0.01-μF on the digital supply terminals.

When placing and connecting all bypass capacitors, follow high-speed board design rules.

6.4.2 Digital Supplies 1.8 V

The TUSB3410 requires a 1.8-V digital power source.

The 3.3-V terminals are named VDD18 and supply power to most of the input and output cells. VDD18 supplies must have 0.1-μF bypass capacitors to VSS (ground) to ensure proper operation. One capacitor per power terminal is sufficient and should be placed as close to the terminal as possible to minimize trace length. TI also recommends smaller value capacitors like 0.01-μF on the digital supply terminals.

When placing and connecting all bypass capacitors, follow high-speed board design rules.

An internal voltage regulator generates this supply voltage when terminal VREGEN is low. When VREGEN is high, 1.8 V must be supplied externally.