SLLS413L February 2000 – June 2017 TUSB2046B , TUSB2046I
PRODUCTION DATA.
The TUSB2046x provides the flexibility of using a 6-MHz or a 48-MHz clock. The logic level of the TSTMODE terminal controls the selection of the clock source. When TSTMODE is low, the output of the internal APLL circuitry is selected to drive the internal core of the device. When TSTMODE is high, the TSTPLL/48MCLK input is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered down while TSTMODE is high. Low EMI emission is achieved because the TUSB2046x can usee a 6-MHz crystal input. Connect the crystal as shown in Figure 6. An internal PLL then generates the 48-MHz clock used to sample data from the upstream port and to synchronize the 12 MHz used for the USB clock. If low-power suspend and resume are desired, a passive crystal or resonator must be used. However, a 6-MHz oscillator may be used by connecting the output to the XTAL1 pin and leaving the XTAL2 pin open. The oscillator TTL output must not exceed 3.6 V.
For 48-MHz operation, the clock cannot be generated with a crystal using the XTAL2 output because the internal oscillator cell supports only the fundamental frequency. Other useful features of the TUSB2046x include a package with a 0.8-mm pin pitch for easy PCB routing and assembly, push-pull outputs for the PWRON pins eliminate the need for pullup resistors required by traditional open-collector I/Os, and OVRCUR pins have noise filtering for increased immunity to voltage spikes.