SLWS224E August   2010  – January 2016 TRF372017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements - SPI: Writing Phase
    6. 6.6 Timing Requirements - SPI: Read-Back Phase
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Integer and Fractional Mode Selection
      2. 7.3.2  Description of PLL Structure
        1. 7.3.2.1 Selecting PLL Divider Values
        2. 7.3.2.2 Setup Example for Integer Mode
        3. 7.3.2.3 Setup Example for Fractional Mode
      3. 7.3.3  Fractional Mode Setup
      4. 7.3.4  Selecting the VCO and VCO Frequency Control
      5. 7.3.5  External VCO
      6. 7.3.6  VCO Test Mode
      7. 7.3.7  Lock Detect
      8. 7.3.8  Tx Divider
      9. 7.3.9  LO Divider
      10. 7.3.10 Mixer
      11. 7.3.11 Disabling Outputs
      12. 7.3.12 Power Supply Distribution
      13. 7.3.13 Carrier Feedthrough Cancellation
      14. 7.3.14 Internal Baseband Bias Voltage Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Powersave Mode
    5. 7.5 Register Maps
      1. 7.5.1 Serial Interface Programming Registers Definition
        1. 7.5.1.1 PLL SPI Registers
          1. 7.5.1.1.1 Register 1
          2. 7.5.1.1.2 Register 2
          3. 7.5.1.1.3 Register 3
          4. 7.5.1.1.4 Register 4
          5. 7.5.1.1.5 Register 5
          6. 7.5.1.1.6 Register 6
          7. 7.5.1.1.7 Register 7
        2. 7.5.1.2 Readback Mode
          1. 7.5.1.2.1 Readback From the Internal Registers Banks
            1. 7.5.1.2.1.1 Register 0 Write
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DAC Interfacing With External Baseband Bias Voltage
        2. 8.2.2.2 DAC Interface Using Internal VCM Generation
        3. 8.2.2.3 LO Outputs
        4. 8.2.2.4 Loop Filter
        5. 8.2.2.5 ESD Sensitivity
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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4 Revision History

Changes from D Revision (September 2013) to E Revision

  • Added Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

Changes from C Revision (May 2012) to D Revision

  • Changed text string from Reg 1, B[30..28] = [000] to Reg 0, B[30..28] = [000] in the Description column associated with RB_REG<0>, RB_REG<1>, and RB_REG<2>Go

Changes from B Revision (March 2012) to C Revision

  • Added graph titles to Figure 56 and 57 that were missing in Revision B.Go

Changes from A Revision (August 2010) to B Revision

  • Deleted Comments column from Table 1Go
  • Changed Figures 12 through Figure 27Go
  • Changed the text under Integer and Fractional Mode Selection through Practical Limit on Maximum PFD Frequency.Go
  • Changed RDIV = 20 to RDIV = 2 in Setup Example for Fractional Mode.Go
  • Changed Recommended Value of EN_LD_ISOURCE from 1 to 0 in Table 1Go
  • Changed column heading from Default Value to Reset Value in register tables 1, 2, 3, 4, 5, 6, and 7Go
  • Added recommended programming [xx] to various Description statements in register tables 2, 5, 6, and 7.Go
  • Changed Register 4, Bit21/Bit22 Description statement from Off to Normal.Go
  • Changed Column heading from Default Value to Reset Value in Readback mode section, Register 0Go
  • Changed Bit5 name from CHIP_ID to CHIP_ID _0 and changed Bit6 name from NU to CHIP_ID_1, Reset Value to 1Go
  • Changed image in Figure 87. Go
  • Changed the text in the Application Layout, and added link to Figure 95Go